公开(公告)号：US20240291488A1

公开(公告)日：2024-08-29

申请号：US18582446

申请日：2024-02-20

Applicant: STMicroelectronics International N.V.

Inventor： Ravinder KUMAR ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/00369 ,  H03K19/017545 ,  H03K19/017581

Abstract: The present disclosure is directed to a voltage driver, where a combination of first and second resistance blocks controls a differential voltage swing on the outputs of the voltage driver. Variations of an input voltage are compensated by adding different values of the first resistance block to the second resistance block, while keeping a summation of the first and second resistance blocks at a constant value. Three different circuit diagrams are disclosed to generate these different resistances. In each circuit diagram, one or more control signals change the resistance of the combination of first and second resistance blocks. In some embodiments, the value of the second resistance block is changed by the first resistance block to maintain an impedance matching between a transmitter and a receiver, while changing of the first resistance block compensates for the differential voltage swing.

公开(公告)号：US20240288557A1

公开(公告)日：2024-08-29

申请号：US18176163

申请日：2023-02-28

Applicant: STMicroelectronics International N.V.

Inventor： Stuart McLeod ,  Andreas Assmann

IPC: G01S7/4865 ,  G01S7/48 ,  G01S17/89

CPC classification number: G01S7/4865 ,  G01S7/4808 ,  G01S17/89

Abstract: A method of determining a distance of a closest target using a time-of-flight (ToF) ranging system includes: receiving, by a processor, a histogram generated by a ToF imager of the ToF ranging system, where the ToF imager is configured to transmit a light pulse for ranging purpose; finding a first rising edge in the histogram that corresponds to a rising edge of a reflected light pulse from the closest target; and calculating a first estimate of the distance of the closest target by adding a pre-determined offset to a distance of the first rising edge.

公开(公告)号：US12073308B2

公开(公告)日：2024-08-27

申请号：US15423279

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/063 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/0464 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78 ,  G06F115/02 ,  G06F115/08 ,  G06N3/04 ,  G06N3/08 ,  G06N7/01

CPC classification number: G06N3/0464 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/44505 ,  G06F13/4022 ,  G06F15/7817 ,  G06F2115/02 ,  G06F2115/08 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N7/01

Abstract: Embodiments are directed towards a hardware accelerator engine that supports efficient mapping of convolutional stages of deep neural network algorithms. The hardware accelerator engine includes a plurality of convolution accelerators, and each one of the plurality of convolution accelerators includes a kernel buffer, a feature line buffer, and a plurality of multiply-accumulate (MAC) units. The MAC units are arranged to multiply and accumulate data received from both the kernel buffer and the feature line buffer. The hardware accelerator engine also includes at least one input bus coupled to an output bus port of a stream switch, at least one output bus coupled to an input bus port of the stream switch, or at least one input bus and at least one output bus hard wired to respective output bus and input bus ports of the stream switch.

公开(公告)号：US12068057B2

公开(公告)日：2024-08-20

申请号：US18056803

申请日：2022-11-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC: G11C7/24 ,  G11C7/10

CPC classification number: G11C7/24 ,  G11C7/1039 ,  G11C7/1069

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

公开(公告)号：US12068048B2

公开(公告)日：2024-08-20

申请号：US17815807

申请日：2022-07-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Vivek Mohan Sharma ,  Roberto Colombo

IPC: G11C29/24 ,  G11C29/36 ,  G11C29/42 ,  G11C29/48

CPC classification number: G11C29/42 ,  G11C29/36 ,  G11C29/48 ,  G11C2029/3602

Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.

公开(公告)号：US20240272004A1

公开(公告)日：2024-08-15

申请号：US18108154

申请日：2023-02-10

Applicant: STMicroelectronics International N.V.

Inventor： Enri DUQI ,  Giorgio ALLEGATO

IPC: G01J5/10 ,  B81B7/00 ,  B81C1/00

CPC classification number: G01J5/10 ,  B81B7/0038 ,  B81B7/007 ,  B81C1/00285 ,  B81C1/00301 ,  B81B2201/0278 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/097 ,  B81C2203/0109 ,  B81C2203/0792 ,  G01J2005/106

Abstract: Disclosed herein is a method of forming a thermal sensor, including patterning an active layer on a first face of a handle substrate to form a frame, a mass carrying at least one thermally isolated MOS (TMOS) transistor, and a spring structure connecting the mass to the frame while thermally isolating the mass from the frame. The frame is then bonded to pads on a first face of an integrated circuit substrate. The handle substrate is removed, and a top cap is bonded to the first face of the integrated circuit substrate to enclose at least the mass and spring within the sealed cavity.

公开(公告)号：US20240266425A1

公开(公告)日：2024-08-08

申请号：US18422867

申请日：2024-01-25

Applicant: STMicroelectronics International N.V.

Inventor： Aurore CONSTANT ,  Ferdinando IUCOLANO ,  Cristina TRINGALI ,  Maria Eloisa CASTAGNA

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L29/66462

Abstract: The present disclosure relates to a method of forming an HEMT transistor, comprising the following successive steps: a) providing a stack comprising a semiconductor channel layer, a semiconductor barrier layer on top of and in contact with the semiconductor channel layer, and a semiconductor gate layer arranged on top of and in contact with the semiconductor barrier layer, the semiconductor gate layer comprising P-type dopant elements; and b) compensating for the P-type doping with oxygen atoms, in an upper portion of the semiconductor gate layer, by an oxygen anneal, so as to define a PN junction at the interface between the upper portion and a central portion of the semiconductor gate layer.

公开(公告)号：US20240266343A1

公开(公告)日：2024-08-08

申请号：US18418051

申请日：2024-01-19

Applicant: STMicroelectronics International N.V.

Inventor： Anuj BHARDWAJ ,  Anand Kumar MISHRA ,  Rohit Kumar GUPTA

IPC: H01L27/02 ,  H01L21/762 ,  H01L23/538 ,  H01L29/06

CPC classification number: H01L27/0207 ,  H01L21/76224 ,  H01L23/5386 ,  H01L29/0607

Abstract: An integrated circuit includes a semiconductor substrate patterned to include a first semiconductor track and a second semiconductor track separated from each other by a trench isolation region. The integrated circuit includes a logic circuit including a transistor having a first drain subregion in the first semiconductor track, a second drain subregion in the second semiconductor track, a first source subregion in the first semiconductor track, and a second source subregion in the second semiconductor track. A diffusion bridge of semiconductor material extends between the first and second semiconductor tracks and connects the first source subregion to the second source subregion. The first drain subregion and the second drain subregion are electrically connected by a drain metalization.

公开(公告)号：US20240265940A1

公开(公告)日：2024-08-08

申请号：US18417588

申请日：2024-01-19

Applicant: STMicroelectronics International N.V.

Inventor： Michele Boscolo Berto ,  Ezio Galbiati

IPC: G11B5/55 ,  G11B19/20 ,  H02P7/025

CPC classification number: G11B5/5569 ,  G11B19/2009 ,  H02P7/025

Abstract: Embodiments provide a method of operating a voice coil motor via a transconductance loop. The method includes detecting an actual value of a supply voltage of the transconductance loop. An offset compensation signal of the transconductance loop is produced as a function of the detected actual value of the supply voltage based on a relationship between offset values and the supply voltage of the transconductance loop. The offset compensation signal is applied to a loop control signal of the transconductance loop. A drive current is applied to the voice coil motor. The drive current is related to a target drive current that is based on the loop control signal.

公开(公告)号：US20240265249A1

公开(公告)日：2024-08-08

申请号：US18105729

申请日：2023-02-03

Applicant: STMicroelectronics International N.V.

Inventor： Danilo Pietro Pau ,  Prem Kumar Ambrose

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: Methods, apparatuses, systems, and computer program products for artificial intelligence and machine learning for resource constrained devices and systems, including for classifier learning from a stream of data. A classifier may include a neural network comprised of a plurality of layers with each layer comprised of a plurality of neurons. The neural network may include a hidden layer comprised of a plurality of hidden neurons. In various embodiments, the size of the hidden layer may be constrained and the training of a hidden layer included removing one or more hidden neurons from the hidden layer.