公开(公告)号：US09946650B2

公开(公告)日：2018-04-17

申请号：US15393921

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Zeev Offen ,  Ariel Berkovits ,  Thomas A. Piazza ,  Robert L. Farrell ,  Altug Koker ,  Opher Kahn

IPC: G06T9/00 ,  G06F12/0831 ,  G06F12/0817 ,  G06F12/0811 ,  G06T1/60 ,  G06F13/42 ,  G11C7/10 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0828 ,  G06F12/0835 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4282 ,  G06F2212/283 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2213/0026 ,  G06T1/60 ,  G11C7/1072

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

公开(公告)号：US09946649B1

公开(公告)日：2018-04-17

申请号：US14755873

申请日：2015-06-30

Applicant: EMC Corporation

Inventor： Assaf Natanzon ,  Steven R. Bromling ,  Joshua C. Baergen ,  Michael Trachtman

IPC: G06F12/00 ,  G06F12/0817

CPC classification number: G06F12/0828 ,  G06F2212/621

Abstract: A method, computer program product, and computing system for defining an IO splitter module within each of a plurality of nodes included within a hyper-converged storage environment. A coherency module is defined on at least one of the plurality of nodes. A data request is received.

公开(公告)号：US09916246B1

公开(公告)日：2018-03-13

申请号：US15238209

申请日：2016-08-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Carson Donahue Henrion ,  Michael K. Ciraula ,  Gregg Donley ,  Alok Garg ,  Eric Busta

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/128

CPC classification number: G06F12/0811 ,  G06F12/0828 ,  G06F12/0833 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70

Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.

公开(公告)号：US20170371787A1

公开(公告)日：2017-12-28

申请号：US15192734

申请日：2016-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Eric Christopher Morton ,  Amit P. Apte ,  Elizabeth M. Cooper

IPC: G06F12/0815 ,  G06F12/0813

CPC classification number: G06F12/0815 ,  G06F9/526 ,  G06F12/0813 ,  G06F12/0828 ,  G06F12/0842 ,  G06F2209/522 ,  G06F2209/523 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/154 ,  G06F2212/284 ,  G06F2212/608 ,  G06F2212/62

Abstract: A system and method for network traffic management between multiple nodes are described. A computing system includes multiple nodes connected to one another. When a home node determines a number of nodes requesting read access for a given data block assigned to the home node exceeds a threshold and a copy of the given data block is already stored at a first node of the multiple nodes in the system, the home node sends a command to the first node. The command directs the first node to forward a copy of the given data block to the home node. The home node then maintains a copy of the given data block and forwards copies of the given data block to other requesting nodes until the home node detects a write request or a lock release request for the given data block.

公开(公告)号：US20170357586A1

公开(公告)日：2017-12-14

申请号：US15180351

申请日：2016-06-13

Applicant: Intel Corporation

Inventor： SAMANTIKA S. SURY ,  ROBERT G. BLANKENSHIP ,  SIMON C. STEELY, JR.

IPC: G06F12/0831

CPC classification number: G06F12/0833 ,  G06F9/52 ,  G06F12/0828 ,  G06F2212/1024 ,  G06F2212/502 ,  G06F2212/621

Abstract: In an embodiment, a processor includes a plurality of cores and synchronization logic. The synchronization logic includes circuitry to: receive a first memory request and a second memory request; determine whether the second memory request is in contention with the first memory request; and in response to a determination that the second memory request is in contention with the first memory request, process the second memory request using a non-blocking cache coherence protocol. Other embodiments are described and claimed.

公开(公告)号：US09830265B2

公开(公告)日：2017-11-28

申请号：US14085106

申请日：2013-11-20

Applicant: NETSPEED SYSTEMS

Inventor： Joe Rowlands ,  Sailesh Kumar

IPC: G06F12/00 ,  G06F12/084 ,  G06F9/50 ,  G06F12/0817 ,  G06F12/0811 ,  G06F12/0815

CPC classification number: G06F12/084 ,  G06F9/50 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/082 ,  G06F12/0826 ,  G06F12/0828

Abstract: The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or more entries having a first format to a single entry having a second format when resources corresponding to the one or more entries are shared by the agents. First format can include an address and a pointer representing one of the agents, and the second format can include a sharing vector indicative of more than one of the agents. In another aspect, the second format can utilize, incorporate, and/or represent multiple entries that may be indicative of one or more resources based on a position in the directory.

公开(公告)号：US09772874B2

公开(公告)日：2017-09-26

申请号：US15010681

申请日：2016-01-29

Applicant: International Business Machines Corporation

Inventor： Fadi Y. Busaba ,  Harold W. Cain, III ,  Michael K. Gschwind ,  Valentina Salapura ,  Eric M. Schwarz ,  Timothy J. Slegel

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/52 ,  G06F12/14 ,  G06F9/30

CPC classification number: G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30189 ,  G06F9/467 ,  G06F9/5038 ,  G06F9/526 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/1416 ,  G06F2212/1052 ,  G06F2212/621

Abstract: A method, system, and computer program product are provided for prioritizing transactions. A processor in a computing environment initiates the execution of a transaction. The processor includes a transactional core, and the execution of the transaction is performed by the transactional core. The processor obtains concurrent with the execution of the transaction by the transactional core, an indication of a conflict between the transaction and at least one other transaction being executed by an additional core in the computing environment. The processor determines if the transactional core includes an indicator and based on determining that the transactional core includes an indicator, the processor ignores the conflict and utilizing the transactional core to complete executing the transaction.

公开(公告)号：US20170220470A1

公开(公告)日：2017-08-03

申请号：US15277770

申请日：2016-09-27

Applicant: International Business Machines Corporation

Inventor： Fadi Y. BUSABA ,  Harold W. CAIN, III ,  Michael K. GSCHWIND ,  Valentina SALAPURA ,  Eric M. SCHWARZ ,  Timothy J. SLEGEL

IPC: G06F12/0817 ,  G06F9/46 ,  G06F12/0831

CPC classification number: G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30189 ,  G06F9/467 ,  G06F9/5038 ,  G06F9/526 ,  G06F12/0284 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/1416 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/621

Abstract: A method, system, and computer program product are provided for prioritizing transactions. A processor in a computing environment initiates the execution of a transaction. The processor includes a transactional core, and the execution of the transaction is performed by the transactional core. The processor obtains concurrent with the execution of the transaction by the transactional core, an indication of a conflict between the transaction and at least one other transaction being executed by an additional core in the computing environment. The processor determines if the transactional core includes an indicator and based on determining that the transactional core includes an indicator, the processor ignores the conflict and utilizing the transactional core to complete executing the transaction.

公开(公告)号：US20170220467A1

公开(公告)日：2017-08-03

申请号：US15492736

申请日：2017-04-20

Applicant: Red Hat, Inc.

Inventor： Filip Eliás ,  Filip Nguyen

IPC: G06F12/0811 ,  G06F12/0817

CPC classification number: G06F12/0811 ,  G06F12/0806 ,  G06F12/0828 ,  G06F12/0891 ,  G06F2212/283 ,  G06F2212/621

Abstract: A cache system stores a number of different datasets. The cache system includes a number of cache units, each in a state associated with one of the datasets. In response to determining that a hit ratio of a cache unit drops below a threshold, the state of the cache unit is changed and the dataset is replaced with that associated with the new state.

公开(公告)号：US09720837B2

公开(公告)日：2017-08-01

申请号：US14317382

申请日：2014-06-27

Applicant: International Business Machines Corporation

Inventor： Jonathan D. Bradbury ,  Michael Karl Gschwind ,  Valentina Salapura ,  Chung-Lung K. Shum

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/52 ,  G06F12/0837 ,  G06F12/0817 ,  G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/0837 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0811 ,  G06F12/0828 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/1041 ,  G06F2212/283 ,  G06F2212/621 ,  G06F2212/622

Abstract: A computer allows non-cacheable loads or stores in a hardware transactional memory environment. Transactional loads or stores, by a processor, are monitored in a cache for TX conflicts. The processor accepts a request to execute a transactional execution (TX) transaction. Based on processor execution of a cacheable load or store instruction for loading or storing first memory data of the transaction, the computer can perform a cache miss operation on the cache. Based on processor execution of a non-cacheable load instruction for loading second memory data of the transaction, the computer can not-perform the cache miss operation on the cache based on a cache line associated with the second memory data being not-cached, and load an address of the second memory data into a non-cache-monitor. The TX transaction can be aborted based on the non-cache monitor detecting a memory conflict from another processor.