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    Method of manufacturing wireless suspension blank
    111.
    发明申请
    Method of manufacturing wireless suspension blank 失效
    制造无线悬挂空白的方法

    公开(公告)号：US20020003127A1

    公开(公告)日：2002-01-10

    申请号：US09900768

    申请日：2001-07-06

    Inventor： Katsuya Sakayori ,  Shigeki Kawano ,  Hiroko Amasaki ,  Kazuo Umeda ,  Satoshi Sasaki ,  Hiroshi Yagi

    IPC: C23F001/00 ,  B44C001/22

    CPC classification number: G11B5/484 ,  C23F1/02 ,  G11B5/486 ,  H05K1/056 ,  H05K3/002 ,  H05K3/064 ,  H05K3/386 ,  H05K2201/0154 ,  H05K2201/0166 ,  H05K2201/0394 ,  H05K2203/0554 ,  H05K2203/0793

    Abstract: A method of manufacturing a wireless suspension blank is a method of manufacturing a wireless blank in which three-layered laminate formed of a metallic layer having the spring property and a conductive layer laminated on the metallic layer through an electrically insulating layer are used, wherein as the laminate used is a laminate in which an insulating layer is formed of core-insulating layer and adhesive layers laminated on both sides of the core-insulating layer, and the ratio of higher etching rate to lower etching rate of the respective layers of the insulating layer is between 6:1 and 1:1. By the photo etching method processed are the metallic layer and the conductive layer. The insulating layer is processed by the wet etching method. Or, a method of manufacturing a wireless suspension blank is a method of manufacturing a wireless suspension blank, in which two-layered laminate formed of a metallic layer having the spring property and a conductive layer laminated on the metallic layer through are used. A laminate is used in which the insulating layer is formed of core-insulating layer and adhesive layer laminated on the core-insulating layer, and the ratio of higher etching rate to a lower etching rate of the respective layers of the insulating layer is between 6:1 and 1:1. By the photo etching method processed is the metallic layer. The insulating layer is processed by the semi-additive method so that the wiring part is formed on the insulating layer, wherein the insulating layer is processed by the wet etching method. Since in both methods, the processing of the insulating layer is made by the wet etching layer, the low cost production is possible. Further, in the latter method, since two-layered laminate is used, the low cost production is possible.

    Abstract translation: 一种制造无线悬挂坯料的方法是使用其中使用由具有弹簧性质的金属层和通过电绝缘层层压在金属层上的导电层形成的三层层压体的无线坯料的方法，其中， 使用的层压体是其中绝缘层由芯绝缘层和层压在芯绝缘层的两侧上的粘合剂层形成的层压体，并且绝缘层的各个层的较高蚀刻速率与较低蚀刻速率的比率 层在6：1和1：1之间。 通过处理的光蚀刻方法是金属层和导电层。 通过湿蚀刻方法处理绝缘层。 或者，制造无线悬挂毛坯的方法是使用其中由具有弹簧性质的金属层和层压在金属层通孔上的导电层形成的两层叠层的无线悬浮毛坯的制造方法。 使用其中绝缘层由芯绝缘层和层压在芯绝缘层上的粘合剂层形成的层压体，并且绝缘层的各个层的较高蚀刻速率与较低蚀刻速率的比率在6 ：1和1：1。 通过光刻蚀方法处理的是金属层。 通过半加法处理绝缘层，使得布线部分形成在绝缘层上，其中通过湿蚀刻方法处理绝缘层。 由于在两种方法中，通过湿式蚀刻层进行绝缘层的处理，因此可以实现低成本生产。 此外，在后一种方法中，由于使用了两层叠层，所以可以实现低成本生产。

    Flexible circuit with conductive vias having off-set axes
    112.
    发明授权
    Flexible circuit with conductive vias having off-set axes 失效
    具有导通孔的柔性电路具有偏置轴

    公开(公告)号：US06211468B1

    公开(公告)日：2001-04-03

    申请号：US09132828

    申请日：1998-08-12

    Applicant: David J. Windschitl

    Inventor： David J. Windschitl

    IPC: H01R909

    CPC classification number: H01L21/486 ,  H01L23/49827 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K3/002 ,  H05K3/388 ,  H05K3/4076 ,  H05K2201/0166 ,  H05K2201/09827 ,  H05K2201/09836 ,  H05K2201/09854 ,  H01L2924/00

    Abstract: A flexible circuit includes a flexible non-conductive substrate having a first surface and a second surface. A first electrically conductive trace is provided on the first surface and a second electrically conductive trace is provided on the second surface. A passage extends through the substrate from an end of the first trace to an end of the second trace. The passage includes a beveled opening of a first size formed in the first side and axially aligned with a second beveled opening of the first size formed in the second side. The first and second openings are interconnected by an aperture axially aligned therewith and being of a second size less than the first size. An electrically conductive surface is provided on the passage for electrically interconnecting the first trace and the second trace.

    Abstract translation: 柔性电路包括具有第一表面和第二表面的柔性非导电基底。 第一导电迹线设置在第一表面上，第二导电迹线设置在第二表面上。 通道从第一迹线的端部延伸穿过基底到第二迹线的末端。 通道包括形成在第一侧中的第一尺寸的斜切开口，并且与形成在第二侧中的第一尺寸的第二斜切开口轴向对准。 第一和第二开口通过与其轴向对齐并且具有小于第一尺寸的第二尺寸的孔相互连接。 在通道上设置导电表面，用于电连接第一迹线和第二迹线。

    Forming via holes in a multilevel substrate in a single step
    120.
    发明授权
    Forming via holes in a multilevel substrate in a single step 失效
    在单级步骤中通过多层衬底中的孔形成

    公开(公告)号：US5227013A

    公开(公告)日：1993-07-13

    申请号：US735572

    申请日：1991-07-25

    Applicant: Nalin Kumar

    Inventor： Nalin Kumar

    IPC: H01L21/48 ,  H05K1/00 ,  H05K3/00 ,  H05K3/40

    CPC classification number: H05K3/0035 ,  H01L21/486 ,  H05K1/0393 ,  H05K2201/0166 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/1338 ,  H05K3/002 ,  H05K3/0041 ,  H05K3/4076 ,  Y10T29/49155

    Abstract: A method for forming via holes in a multilayer structure in a single step. The invention includes disposing over a base a first layer comprising first metal lines beneath a first dielectric, disposing over the first layer a second layer comprising second metal lines beneath a second dielectric such that a portion of each first metal line is not beneath any second metal line, and forming via holes which extend through the second dielectric to the second metal lines and through the second dielectric and the first dielectric to the portions of the first metal lines. Thereafter conductive metal can be deposited in the via holes. The method is particularly well suited for fabricating copper/polymer substrates.

    Abstract translation: 一种在一个步骤中在多层结构中形成通孔的方法。 本发明包括在基底上设置包括在第一电介质下方的第一金属线的第一层，在第一层上设置第二层，第二层包括第二电介质下面的第二金属线，使得每个第一金属线的一部分不在任何第二金属之下 并且形成通过第二电介质延伸到第二金属线并且通过第二电介质和第一电介质延伸到第一金属线的部分的通孔。 此后，导电金属可以沉积在通孔中。 该方法特别适用于制造铜/聚合物基材。

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