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    Hard disk drive suspension with integral flexible circuit
    111.
    发明申请
    Hard disk drive suspension with integral flexible circuit 失效

    公开(公告)号：US20030053258A1

    公开(公告)日：2003-03-20

    申请号：US10259005

    申请日：2002-09-27

    Inventor： Christopher G. Dunn ,  Nathan P. Kreutter

    IPC: G11B005/48

    CPC classification number: H05K1/0281 ,  G11B5/4826 ,  G11B5/484 ,  H05K1/056 ,  H05K3/108 ,  H05K3/243 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/2009

    Abstract: A disk drive suspension assembly including an elongated polymeric base member having a plurality of traces formed directly on a first surface thereof and a reference voltage layer formed on a second surface thereof. A support member is formed directly on at least a portion of the reference voltage layer. The plurality of traces overlay at least a portion of the reference voltage layer. The reference voltage layer is formed from a first electrically conductive material and the support member is formed from a second electrically conductive material. The first electrically conductive material providing substantially greater electrical conductivity and substantially less tensile strength than the second electrically conductive material. The support member includes a head gimbal portion having a first thickness and a load beam portion having a second thickness. The second thickness is substantially greater than the first thickness.

    Hard disk drive suspension with integral flexible circuit
    112.
    发明授权
    Hard disk drive suspension with integral flexible circuit 失效
    具有集成柔性电路的硬盘驱动器悬架

    公开(公告)号：US06480359B1

    公开(公告)日：2002-11-12

    申请号：US09567783

    申请日：2000-05-09

    Applicant: Christopher G. Dunn ,  Nathan P. Kreutter

    Inventor： Christopher G. Dunn ,  Nathan P. Kreutter

    IPC: G11B2116

    CPC classification number: H05K1/0281 ,  G11B5/4826 ,  G11B5/484 ,  H05K1/056 ,  H05K3/108 ,  H05K3/243 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/2009

    Abstract: A disk drive suspension assembly including an elongated polymeric base member having a plurality of traces formed directly on a first surface thereof and a reference voltage layer formed on a second surface thereof. A support member is formed directly on at least a portion of the reference voltage layer. The plurality of traces overlay at least a portion of the reference voltage layer. The reference voltage layer is formed from a first electrically conductive material and the support member is formed from a second electrically conductive material. The first electrically conductive material providing substantially greater electrical conductivity and substantially less tensile strength than the second electrically conductive material. The support member includes a head gimbal portion having a first thickness and a load beam portion having a second thickness. The second thickness is substantially greater than the first thickness.

    Abstract translation: 一种磁盘驱动器悬架组件，其包括细长的聚合物基底构件，其具有直接形成在其第一表面上的多个迹线和在其第二表面上形成的参考电压层。 支撑构件直接形成在参考电压层的至少一部分上。 多个迹线覆盖参考电压层的至少一部分。 参考电压层由第一导电材料形成，并且支撑构件由第二导电材料形成。 第一导电材料提供比第二导电材料显着更大的导电性和显着更小的拉伸强度。 支撑构件包括具有第一厚度的头部万向节部分和具有第二厚度的负载梁部分。 第二厚度基本上大于第一厚度。

    Lamination of circuit sub-elements while assuring registration
    113.
    发明授权
    Lamination of circuit sub-elements while assuring registration 失效
    电路子元件的层叠，同时确保注册

    公开(公告)号：US06409930B1

    公开(公告)日：2002-06-25

    申请号：US09432475

    申请日：1999-11-01

    Applicant: Donald A. Whitehurst ,  Paul D. Wyatt ,  Jose F. Brenes ,  Jeffrey M. Borning ,  Bruce A. Finger

    Inventor： Donald A. Whitehurst ,  Paul D. Wyatt ,  Jose F. Brenes ,  Jeffrey M. Borning ,  Bruce A. Finger

    IPC: H01B1300

    CPC classification number: H05K3/067 ,  C23F1/02 ,  C23F1/36 ,  C23F1/44 ,  H01L21/32134 ,  H05K3/061 ,  H05K3/4685 ,  H05K2201/0338 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/1476

    Abstract: A process for the formation of an article having multiple electrical circuits comprises: providing a first sub-element comprising in sequence a first metal layer of copper in electrical contact with a second metal layer of aluminum in electrical contact with a third metal layer of copper; etching an electrical circuit design in the first metal layer and in a separate etch step, etching away at least 10%, but less than 100% of the second metal layer to provide electrical connections between the first metal layer and the third metal layer; etching an electrical circuit design into the third metal layer; adhering an etched surface comprising the circuit design of the first or third metal layer to a first surface of a support layer to form a circuit board. The process may etch the first and third metal layers simultaneously or sequentially. After adhering an etched surface comprising the circuit design of the first or third metal layer in registration to a support layer to form a circuit board, an additional step may be performed, which additional step is selected from the group consisting of: a) adhering an etched surface of a second tri-metal subelement to a second surface of the support layer and b) adhering a second support layer to said third or first metal layer, respectively, and adhering an etched surface of a second tri-metal subelement to the second support layer. The registration between layers may be effected by visual, mechanical, optical or electronic systems with visually or mechanically readable registration marks, radiation through holes, and/or posts used for identifying positions of desired registration between layers.

    Abstract translation: 用于形成具有多个电路的制品的方法包括：提供第一子元件，其顺序地包括与第三金属铜层电接触的与铝的第二金属层电接触的第一金属铜层; 在第一金属层中蚀刻电路设计，并且在单独的蚀刻步骤中，蚀刻掉第二金属层的至少10％但小于100％，以提供第一金属层和第三金属层之间的电连接;蚀刻 将电路设计成第三金属层;将包含第一或第三金属层的电路设计的蚀刻表面粘附到支撑层的第一表面以形成电路板。 该方法可以同时或顺序蚀刻第一和第三金属层。 在将包括第一或第三金属层的电路设计的蚀刻表面粘附到支撑层以形成电路板之后，可以执行附加步骤，该附加步骤选自以下组中：a） 将第二三金属子元件的蚀刻表面分别提供到支撑层的第二表面，b）分别将第二支撑层粘附到所述第三或第一金属层，并将第二三金属子元件的蚀刻表面粘附到第二支撑 层之间的配准可以通过视觉，机械，光学或电子系统实现，其具有用于识别层之间期望的配准位置的视觉或机械可读配准标记，辐射通孔和/或柱。

    Method of making a parallel capacitor laminate
    114.
    发明申请
    Method of making a parallel capacitor laminate 失效
    制造并联电容层压板的方法

    公开(公告)号：US20020054471A1

    公开(公告)日：2002-05-09

    申请号：US10043830

    申请日：2002-01-09

    Applicant: International Business Machines Corporation

    Inventor： Sylvia Adae-Amoakoh ,  John M. Lauffer ,  Michael D. Lowell ,  Voya R. Markovich ,  Joseph J. Sniezek

    IPC: H01G004/35

    CPC classification number: H05K1/053 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/162 ,  H05K3/403 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0338 ,  H05K2201/0919 ,  H05K2201/10378 ,  H05K2203/0315 ,  Y10T29/417 ,  H01L2924/00

    Abstract: A parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an interconnector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer's outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.

    Abstract translation: 能够形成较大的电路板或类似结构的内部部分以提供电容的并联电容器结构。 或者，电容器可以用作互连器以互连两个不同的电子部件（例如，芯片载体，电路板，甚至半导体芯片），同时仍然为一个或多个所述部件提供期望的电容水平。 电容器包括至少一个内部导电层，在内部导体的相对侧上添加两个附加的导体层，以及无机介电材料（优选地，在第二导体层的外表面上的氧化物层或适用于诸如钛酸钡的适当介电材料 第二导体层）。 此外，电容器包括无机介电材料顶部的外部导体层，从而在内部和附加的导电层和外部导体之间形成并联的电容器。

    Lead-free printed circuit assembly
    116.
    发明授权
    Lead-free printed circuit assembly 失效
    无铅印刷电路组件

    公开(公告)号：US5536908A

    公开(公告)日：1996-07-16

    申请号：US534370

    申请日：1995-09-27

    Applicant: Richard K. Etchells ,  Lawrence E. Tawyea

    Inventor： Richard K. Etchells ,  Lawrence E. Tawyea

    IPC: H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/28 ,  H05K3/34 ,  H05K3/42 ,  H05K1/11

    CPC classification number: H05K3/244 ,  H05K3/062 ,  H05K3/3463 ,  H05K2201/0338 ,  H05K3/108 ,  H05K3/28 ,  H05K3/427

    Abstract: A printed circuit is provided that is capable of operating at temperatures above 200.degree. C. A printed wiring board has a plating scheme of Tin plating over sulfamate nickel plated over copper. The materials are electroplated in the pattern of the desired circuit. The copper provides a conductive material for carrying electrical current. The sulfamate nickel is a ductile material that serves as a barrier between the copper and the Tin and is able to maintain its strength under temperatures of above 200.degree. C. The Tin is compatible with the new solder compound that is used to solder electrical components to the board. The solder compound is comprised of Tin and Silver. This solder has a higher initial melting point than traditional Tin/Lead solders but has a lower solder reflow temperature than conventional HMP solder compounds. This new solder is also stronger than conventional HMP solder and contains virtually no Lead component. A multilayer printed circuit is also provided that has a "Pads Only" design in which only the pads and short runs connecting to vias are allowed on the outer layers of the board. All power and signal runs are restricted to the inner layers of the board. This design has the advantage of protecting the runs in a high temperature environment and results in a more reliable assembly. The multilayer circuit uses the same plating scheme as in the above-described printed circuit.

    Abstract translation: 提供能够在高于200℃的温度下工作的印刷电路。印刷电路板具有通过铜上镀上氨基磺酸镍的镀锡方案。 材料以期望电路的图案电镀。 铜提供用于承载电流的导电材料。 氨基磺酸镍是用作铜和锡之间的屏障的延性材料，能够在高于200℃的温度下保持其强度。锡与用于焊接电气部件的新焊料化合物相容 董事会。 焊锡化合物由锡和银构成。 该焊料具有比传统锡/铅焊料更高的初始熔点，但是具有比常规HMP焊料化合物更低的焊料回流温度。 这种新焊料也比传统的HMP焊料更强，并且几乎没有铅组分。 还提供了一种具有“仅Pads”设计的多层印刷电路，其中仅允许在板的外层上连接通孔的焊盘和短路。 所有电源和信号运行仅限于电路板的内层。 该设计具有在高温环境中保护运行并且导致更可靠的组装的优点。 多层电路使用与上述印刷电路相同的电镀方案。

    Circuit board heat dissipation layering arrangement
    117.
    发明授权
    Circuit board heat dissipation layering arrangement 失效
    电路板散热分层布置

    公开(公告)号：US5375039A

    公开(公告)日：1994-12-20

    申请号：US127150

    申请日：1993-09-27

    Applicant: Thomas Wiesa

    Inventor： Thomas Wiesa

    IPC: H05K1/02 ,  H05K3/42 ,  H05K7/20 ,  H05H7/20

    CPC classification number: H05K1/0206 ,  H05K7/205 ,  H05K1/0272 ,  H05K2201/0338 ,  H05K2201/09054 ,  H05K2201/09745 ,  H05K3/0061 ,  H05K3/42

    Abstract: A circuit board layering arrangement is capable of dissipating, into a heat sink, the heat produced by power components mounted on the circuit board, without permitting the short circuiting of electricity between the power components and other components or the heat sink. The arrangement comprises a circuit board, at least one power component and a heat sink. A plurality of through contacts are introduced into the circuit board, and a plurality of conductive tracks are disposed on first and second surfaces of the circuit board. The plurality of conductive tracks include two large-surface conductive tracks, one on each surface of the circuit board. One or more power components are surface-mounted on a first surface of the circuit board on a first large-surface conductive track. The second large-surface conductive track is thermally coupled to the first large-surface conductive track and to the heat sink. A layer of metal, preferably copper, may be disposed between the second large-surface conductive track and the heat sink, and a layer of glass cloth may be disposed between the second large-surface conductive track and the layer of metal.

    Abstract translation: 电路板层叠装置能够将安装在电路板上的功率部件产生的热量散发到散热器中，而不会使功率部件和其它部件或散热器之间的电短路。 该装置包括电路板，至少一个功率部件和散热器。 多个贯通接点被引入到电路板中，并且多个导电轨道设置在电路板的第一和第二表面上。 多个导电轨道包括两个大表面导电轨道，一个在电路板的每个表面上。 一个或多个功率部件被表面安装在第一大表面导电轨道上的电路板的第一表面上。 第二大表面导电轨道热耦合到第一大表面导电轨道和散热器。 可以在第二大表面导电轨道和散热器之间设置金属层，优选铜层，并且可以在第二大表面导电轨道和金属层之间设置一层玻璃布。

    Circuit board material and electroplating bath for the production thereof
    119.
    发明授权
    Circuit board material and electroplating bath for the production thereof 失效
    电路板材料和电镀浴用于生产

    公开(公告)号：US4892776A

    公开(公告)日：1990-01-09

    申请号：US091990

    申请日：1987-09-02

    Applicant: James H. Rice

    Inventor： James H. Rice

    IPC: C23F1/02 ,  C25D3/56 ,  H01C17/16 ,  H05K1/16 ,  H05K3/06 ,  H05K3/38

    CPC classification number: C25D3/562 ,  C23F1/02 ,  H01C17/16 ,  H05K1/167 ,  H05K3/067 ,  H05K3/384 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2203/0361 ,  H05K2203/0392 ,  H05K2203/0723 ,  H05K2203/124 ,  Y10S205/92 ,  Y10S428/901 ,  Y10T428/12778 ,  Y10T428/24917

    Abstract: An improved circuit board material having a support layer, an electrical resistance layer and a conductive layer. The circuit board material has a resistance of at least about 500 ohms/square. The circuit board material is formed by electro-plating the electrical resistance layer on the conductive layer. The conductive layer is desirably activated prior to electro-deposition of the electrical resistance layer thereon. The conductive layer is activated by contacting with an activating agent such as benzotriazole electrolytic chromate and the like. A preferred electro-plating bath for electro-deposition of the electrical resistance layer comprises about 0.5 mole per liters nickel hypophosphite. The disclosed electro-plating bath functions at ambient temperatures and is effectively temperature independent. Circuit boards can be formed from the circuit board material through a process involving only two etching steps.

    Abstract translation: 一种具有支撑层，电阻层和导电层的改进的电路板材料。 电路板材料具有至少约500欧姆/平方的电阻。 电路板材料通过电导电层上的电阻层而形成。 在其上的电阻层电沉积之前，期望激活导电层。 导电层通过与活化剂如苯并三唑电解铬酸盐等接触来活化。 用于电沉积电阻层的优选电镀浴包含约0.5摩尔/升次磷酸镍。 所公开的电镀浴在环境温度下起作用并且有效地与温度无关。 电路板可以通过仅涉及两个蚀刻步骤的工艺从电路板材料形成。

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