公开(公告)号：US08664536B2

公开(公告)日：2014-03-04

申请号：US13153590

申请日：2011-06-06

Applicant: Masahiro Sunohara ,  Shigeaki Suganuma

Inventor： Masahiro Sunohara ,  Shigeaki Suganuma

IPC: H05K1/09

CPC classification number: H01L23/49822 ,  H01L23/147 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/388 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/10378 ,  H01L2924/00

Abstract: A wiring substrate includes a wiring layer made of copper, an electrode layer made of copper, and an insulating layer arranged adjacent to the electrode layer. The wiring layer is stacked on the electrode layer and the insulating layer. The insulating layer and the wiring layer are stacked with an adhesive layer interposed between the insulating layer and the wiring layer. The electrode layer and the wiring layer are stacked with a copper alloy layer formed adjacent to the adhesive layer and interposed between the electrode layer and the wiring layer.

Abstract translation: 布线基板包括由铜制成的布线层，由铜制成的电极层和与电极层相邻布置的绝缘层。 布线层堆叠在电极层和绝缘层上。 绝缘层和布线层被叠置在介于绝缘层和布线层之间的粘合剂层。 电极层和布线层与形成在粘合剂层附近的铜合金层层叠，插入在电极层和布线层之间。

公开(公告)号：US20130328070A1

公开(公告)日：2013-12-12

申请号：US13828895

申请日：2013-03-14

Applicant: CREE, INC.

Inventor： Christopher P. Hussell ,  Jesse Colin Reiherzer ,  Erin Welch

IPC: H01L33/62

CPC classification number: H01L33/62 ,  H01L25/0753 ,  H01L33/60 ,  H01L33/641 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2933/0033 ,  H05K3/244 ,  H05K2201/0341 ,  H05K2201/099 ,  H05K2201/10106 ,  H05K2201/2054 ,  H05K2203/073 ,  H05K2203/1461 ,  H01L2924/00014

Abstract: Light emitting devices and substrates are provided with improved plating. In one embodiment, a light emitting device can include a submount and one or more light emitting diodes (LED) chips disposed over the submount. In one embodiment, the submount can include a copper (Cu) substrate, a first metallic layer of material that is highly reflective disposed over the Cu substrate for increased brightness of the device, and a second metallic layer disposed between the Cu substrate and the first metallic layer for forming a barrier therebetween.

Abstract translation: 发光器件和衬底具有改进的电镀。 在一个实施例中，发光器件可以包括底座和设置在所述底座上方的一个或多个发光二极管（LED）芯片。 在一个实施例中，底座可以包括铜（Cu）衬底，高度反射性地设置在Cu衬底上的用于增加器件亮度的第一金属材料层，以及设置在Cu衬底和第一衬底之间的第二金属层 用于在其间形成屏障的金属层。

公开(公告)号：US20130256014A1

公开(公告)日：2013-10-03

申请号：US13993463

申请日：2011-12-02

Applicant: Naoto Takahashi ,  Yasuyuki Yamamoto ,  Emi Ushioda

Inventor： Naoto Takahashi ,  Yasuyuki Yamamoto ,  Emi Ushioda

IPC: H05K3/06 ,  H05K1/09

CPC classification number: H05K3/06 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/108 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0341 ,  Y10T428/24967 ,  Y10T428/265

Abstract: The present invention provides: a method for manufacturing a metallized substrate by which a fine pattern can be formed more easily; a metallized substrate manufactured by the method; and a metal paste composition to be used in the method. The metallized substrate has: a sintered nitride ceramic substrate (10); a titanium nitride layer (20) on the sintered substrate (10); an adhesion layer (30) on the titanium nitride layer (20); and a copper plating layer (40) on or above the adhesion layer (30), wherein the adhesion layer (30) contains copper and titanium, and has a thickness of no less than 0.1 μm and no more than 5 μm.

Abstract translation: 本发明提供一种金属化基板的制造方法，能够更容易地形成精细图案， 通过该方法制造的金属化基板; 以及该方法中使用的金属糊剂组合物。 金属化基板具有：烧结氮化物陶瓷基板（10）; 在所述烧结基板（10）上的氮化钛层（20）; 在氮化钛层上的粘合层（30）; 以及在所述粘合层（30）上或上方的铜镀层（40），其中所述粘合层（30）含有铜和钛，并且具有不小于0.1μm且不大于5μm的厚度。

公开(公告)号：US08476536B2

公开(公告)日：2013-07-02

申请号：US11987617

申请日：2007-12-03

Applicant: Kentaro Kaneko ,  Kotaro Kodani ,  Junichi Nakamura ,  Kazuhiro Kobayashi

Inventor： Kentaro Kaneko ,  Kotaro Kodani ,  Junichi Nakamura ,  Kazuhiro Kobayashi

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/0341 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A wiring substrate has pads formed from a plurality of metal layers and vias connected to the pads. The plurality of metal layers have a metal layer exposed through the wiring substrate, and a first metal layer which is interposed between the metal layer and the vias and which prevents diffusion of metal included in the vias into the metal layer. A second metal layer which is less subject to oxidation than the first metal layer is provided between the vias and the first metal layer, and the vias are connected to the second metal layer.

Abstract translation: 布线基板具有由多个金属层形成的焊盘和连接到焊盘的通孔。 多个金属层具有通过布线基板露出的金属层，以及介于金属层和通孔之间的第一金属层，并且防止通孔中包含的金属扩散到金属层中。 在通孔和第一金属层之间设置有比第一金属层更少受到氧化的第二金属层，并且通孔连接到第二金属层。

公开(公告)号：US20120181688A1

公开(公告)日：2012-07-19

申请号：US13355311

申请日：2012-01-20

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H01L23/498

CPC classification number: H01L24/00 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13171 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/099 ,  H05K2203/054 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Abstract translation: 提供一种具有导电结构的封装基板，包括其表面上具有至少一个导电焊盘的基板主体，设置在导电焊盘上的应力缓冲金属层，应力缓冲金属层的厚度为1-20μm， 防焊层设置在基板主体上并且在其中具有至少一个开口，用于相应地暴露应力缓冲金属层的顶表面的一部分，设置在应力缓冲金属层的表面的中心部分上的金属柱，以及 焊料凸块覆盖金属柱的表面。 因此，通过使用应力缓冲金属层来释放热应力，并且使用金属柱和焊料凸块来增加导电结构的高度，提供了高度可靠的导电结构。

公开(公告)号：US20120152597A1

公开(公告)日：2012-06-21

申请号：US13325767

申请日：2011-12-14

Applicant: Erina YAMADA ,  Kazunaga HIGO ,  Hironori SATO

Inventor： Erina YAMADA ,  Kazunaga HIGO ,  Hironori SATO

IPC: H05K1/09 ,  B23K31/02 ,  H05K3/00

CPC classification number: B23K1/0016 ,  B23K2101/42 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16225 ,  H05K3/244 ,  H05K3/3473 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2203/054

Abstract: A wiring board including a conductor post corresponding to high-density packaging is provided. The wiring board may comprise a conductor layer, a solder resist layer laminated on the conductor layer, and a conductor post that is electrically connected to a conductor layer which is disposed in a lower portion of a through-hole provided in the solder resist layer, wherein the solder resist layer comprises a thermosetting resin; the conductor post comprises tin, copper, or a solder; the conductor post includes a lower conductor post, which is located within the through-hole and includes an external side surface and a lower end surface, and an upper conductor post, which is located above the lower conductor post and is projected outside the solder resist layer; and at least a part of a lower end surface of the upper conductor post is brought into intimate contact with an outer surface of the solder resist layer.

Abstract translation: 提供了包括对应于高密度封装的导体柱的布线板。 布线基板可以包括导体层，层叠在导体层上的阻焊层，以及导体柱，其电连接到布置在设置在阻焊层中的通孔的下部的导体层， 其中所述阻焊层包含热固性树脂; 导体柱包括锡，铜或焊料; 导体柱包括位于通孔内并包括外侧表面和下端表面的下导体柱和位于下导体柱上方并被突出在阻焊层外侧的上导体柱 层; 并且上导体柱的下端表面的至少一部分与阻焊层的外表面紧密接触。

公开(公告)号：US20120113547A1

公开(公告)日：2012-05-10

申请号：US13317599

申请日：2011-10-24

Applicant: Yuu Sugimoto

Inventor： Yuu Sugimoto

IPC: G11B5/48

CPC classification number: H05K1/11 ,  G11B5/486 ,  H05K1/0268 ,  H05K1/056 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2203/0323

Abstract: A suspension board with circuit includes a metal supporting board; an insulating layer formed on the metal supporting board having an opening penetrating in the thickness direction formed therein; and a conductive pattern formed on the insulating layer including an external-side terminal electrically connected to an external board. The external-side terminal is filled in the opening of the insulating layer. In the metal supporting board, a support terminal electrically insulated from the surrounding metal supporting board and electrically connected to the external-side terminal is provided. The suspension board with circuit includes a metal plating layer formed below the support terminal and an electrically-conductive layer interposed between the support terminal and the metal plating layer having a thickness of 10 nm or more to 200 nm or less.

Abstract translation: 具有电路的悬挂板包括金属支撑板; 绝缘层，形成在所述金属支撑板上，具有沿其形成的厚度方向贯通的开口; 以及形成在绝缘层上的导电图案，包括与外部电路电连接的外侧端子。 外侧端子填充在绝缘层的开口部中。 在金属支撑板中，设置有与周围金属支撑板电绝缘并与外部侧端子电连接的支撑端子。 具有电路的悬挂板包括形成在支撑端子下方的金属镀层和插入在支撑端子和金属镀层之间的厚度为10nm以上至200nm以下的导电层。

公开(公告)号：US20090144972A1

公开(公告)日：2009-06-11

申请号：US12047936

申请日：2008-03-13

Applicant: David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

Inventor： David C. H. Cheng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

IPC: H05K3/02

CPC classification number: H05K3/4007 ,  H05K3/06 ,  H05K3/062 ,  H05K3/107 ,  H05K3/3452 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/099 ,  H05K2203/0384 ,  H05K2203/0542 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.

Abstract translation: 提供一种制造电路板的工艺。 在该过程中，首先，提供包括绝缘层和至少与绝缘层接触的焊盘的电路基板。 接下来，在电路基板上形成阻挡材料层。 阻挡材料层完全覆盖绝缘层和垫。 然后，在阻挡材料层上形成至少一个导电凸块。 导电凸块与焊盘相对，并且阻挡材料层的材料与导电凸块的材料不同。 接下来，通过使用导电凸块作为掩模来去除阻挡材料层的一部分，以暴露绝缘层的表面并形成连接在导电凸块和焊盘之间的阻挡层。

公开(公告)号：US20090038838A1

公开(公告)日：2009-02-12

申请号：US12188551

申请日：2008-08-08

Applicant: Chia-Wei Chang

Inventor： Chia-Wei Chang

IPC: H01R12/04 ,  H05K3/00

CPC classification number: H05K3/4661 ,  H05K3/108 ,  H05K3/243 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/386 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2203/0353 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/1152 ,  Y10T29/49124

Abstract: A circuit board and a method for fabricating the same are provided. The circuit board includes a core board, a first bonding layer disposed on the core board, and a first wiring layer disposed on the first bonding layer. The first bonding layer enables the first wiring layer to be bonded to the core layer better, thereby preventing delamination and forming a fine-pitch wiring layer.

Abstract translation: 提供一种电路板及其制造方法。 电路板包括芯板，设置在芯板上的第一接合层和设置在第一接合层上的第一布线层。 第一接合层能够使第一布线层更好地与芯层接合，从而防止分层并形成细间距布线层。

公开(公告)号：US20080149383A1

公开(公告)日：2008-06-26

申请号：US11987617

申请日：2007-12-03

Applicant: Kentaro Kaneko ,  Kotaro Kodani ,  Junichi Nakamura ,  Kazuhiro Kobayashi

Inventor： Kentaro Kaneko ,  Kotaro Kodani ,  Junichi Nakamura ,  Kazuhiro Kobayashi

IPC: H05K1/09 ,  H05K3/10 ,  H05K1/11

CPC classification number: H05K1/113 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/0341 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A wiring substrate has pads formed from a plurality of metal layers and vias connected to the pads. The plurality of metal layers have a metal layer exposed through the wiring substrate, and a first metal layer which is interposed between the metal layer and the vias and which prevents diffusion of metal included in the vias into the metal layer. A second metal layer which is less subject to oxidation than the first metal layer is provided between the vias and the first metal layer, and the vias are connected to the second metal layer.

Abstract translation: 布线基板具有由多个金属层形成的焊盘和连接到焊盘的通孔。 多个金属层具有通过布线基板露出的金属层，以及介于金属层和通孔之间的第一金属层，并且防止通孔中包含的金属扩散到金属层中。 在通孔和第一金属层之间设置有比第一金属层更少受到氧化的第二金属层，并且通孔连接到第二金属层。