公开(公告)号：US20040046006A1

公开(公告)日：2004-03-11

申请号：US10609955

申请日：2003-06-30

Inventor： Lars-Anders Olofsson

IPC: B23K031/00 ,  B23K031/02

CPC classification number: H05K3/4046 ,  H05K1/0204 ,  H05K3/4623 ,  H05K2201/0347 ,  H05K2201/0382 ,  H05K2201/10234 ,  H05K2201/10416

Abstract: A method of providing thermal vias in a printed circuit board that includes one or more layers of board material is disclosed. The vias provide for conducting heat from components mounted on the board. One or more holes (4) are provided in a printed circuit board that may include several metal layers. A metal ball (6) is inserted into each hole and subjected to pressure such as to deform said ball, and tightly fixating the resultant slug against the wall (5) of said hole. The deformed ball or slug fixed in the hole, which may have a metallised inner surface, functions to conduct heat and/or electricity between a metallised topside (2) and bottom side (3) of the printed circuit board and also between intermediate metallised layers in the case of a multi-layer board.

Abstract translation: 公开了一种在包括一层或多层板材的印刷电路板中提供热通孔的方法。 通孔提供从安装在电路板上的组件传导热量。 一个或多个孔（4）设置在可包括若干金属层的印刷电路板中。 将金属球（6）插入每个孔中并施加压力以使所述球变形，并将所得的块塞紧紧地固定在所述孔的壁（5）上。 固定在孔中的可能具有金属化内表面的变形的球或块被用来在印刷电路板的金属化顶部（2）和底侧（3）之间以及中间金属化层之间传导热和/或电 在多层板的情况下。

公开(公告)号：US20040045737A1

公开(公告)日：2004-03-11

申请号：US10640272

申请日：2003-08-14

Applicant: SONY CHEMICALS CORP.

Inventor： Hiroyuki Hishinuma ,  Hideyuki Kurita ,  Ryo Ito ,  Masayuki Nakamura

IPC: H05K001/00

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/423 ,  H05K3/4647 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0759 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: A process for manufacturing a flexible wiring board according to the present invention comprises growing metal bumps 16 using a mask film patterned by photolithography. Fine openings can be formed with good precision, therefore, fine metal bumps 16 can be formed with good precision because laser beam is not used to form openings in a polyimide film. After metal bumps 16 have been formed, the mask film is removed and a liquid resin material is applied and dried to form a coating, which is then cured into a resin film. The coating can be etched at surface portions during coating stage to expose the tops of metal bumps 16.

Abstract translation: 根据本发明的制造柔性布线板的方法包括使用通过光刻图案化的掩模膜生长金属凸块16。 可以精确地形成精细的开口，因此，由于激光束不用于在聚酰亚胺膜中形成开口，所以可以以高精度形成精细的金属凸块16。 在形成金属凸块16之后，去除掩模膜并施加液态树脂材料并干燥以形成涂层，然后将其固化成树脂膜。 可以在涂覆阶段期间在表面部分蚀刻涂层以暴露金属凸块16的顶部。

公开(公告)号：US20040009335A1

公开(公告)日：2004-01-15

申请号：US10615067

申请日：2003-07-09

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Toshifumi Kojima ,  Makoto Wakazono ,  Toshikatu Takada

IPC: B32B003/00 ,  B32B015/00 ,  B65B001/00

CPC classification number: H05K3/0094 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0959 ,  Y10S428/901 ,  Y10T156/10 ,  Y10T428/24893 ,  Y10T428/24917 ,  Y10T428/25

Abstract: A solvent-free filling material comprising a filler, a thermosetting resin, a curing agent, and a curing catalyst, wherein the thermosetting resin is an epoxy resin, and the curing agent is a dicyandiamide curing agent; a multilayer printed wiring board comprising a substrate, a through-hole, the filling material filling the through-hole, and a conductor layer formed on an exposed surface of the filling material in the through-hole; and a process for producing the multilayer printed wiring board.

Abstract translation: 一种无溶剂填充材料，包括填料，热固性树脂，固化剂和固化催化剂，其中热固性树脂是环氧树脂，固化剂是双氰胺固化剂; 包括基板，通孔，填充通孔的填充材料和形成在通孔中的填充材料的暴露表面上的导体层的多层印刷线路板; 以及多层印刷布线板的制造方法。

公开(公告)号：US06643923B1

公开(公告)日：2003-11-11

申请号：US09744572

申请日：2001-02-28

Applicant: Hiroyuki Hishinuma ,  Hideyuki Kurita ,  Ryo Ito ,  Masayuki Nakamura

Inventor： Hiroyuki Hishinuma ,  Hideyuki Kurita ,  Ryo Ito ,  Masayuki Nakamura

IPC: H05K302

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/423 ,  H05K3/4647 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0759 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: A process for manufacturing a flexible wiring board according to the present invention includes growing metal bumps (16) using a mask film patterned by photolithography. Fine openings are formed in a polyimide film with good precision allowing fine metal bumps (16) to be formed with good precision. After metal bumps (16) have been formed, the mask film is removed and a liquid resin material is applied and dried to form a coating, which is then cured into a resin film. The coating can be etched at surface portions during coating stage to expose the tops of metal bumps (16).

Abstract translation: 根据本发明的柔性线路板的制造方法包括使用通过光刻图案化的掩模膜生长金属凸块（16）。 在聚酰亚胺膜中形成精细的开口，精度高，能够精确地形成精细的金属凸块（16）。 在形成金属凸块（16）之后，除去掩模膜并施加液体树脂材料并干燥以形成涂层，然后将其固化成树脂膜。 涂层可以在涂覆阶段在表面部分进行蚀刻以暴露金属凸块（16）的顶部。

公开(公告)号：US06581280B2

公开(公告)日：2003-06-24

申请号：US10197125

申请日：2002-07-17

Applicant: Brian Eugene Curcio ,  Peter Alfred Gruber ,  Frederic Maurer ,  Konstantinos I. Papathomas ,  Mark David Poliks

Inventor： Brian Eugene Curcio ,  Peter Alfred Gruber ,  Frederic Maurer ,  Konstantinos I. Papathomas ,  Mark David Poliks

IPC: H05K330

CPC classification number: H05K3/4069 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4602 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0126 ,  H05K2203/085 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/53191 ,  H01L2924/00

Abstract: High aspect ratio (5:1-30:1) and small (5 &mgr;m-125 &mgr;m) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.

Abstract translation: 提供介电基片中的高纵横比（5：1-30：1）和小（5毫米-125毫米）直径的孔，填充有凝固的导电材料，以及使用压力填充这些孔的方法 和真空。 在某些实施例中，孔用导电材料衬里和/或用导电材料封盖。 本发明还考虑由这种材料形成的芯片载体。

公开(公告)号：US06565917B1

公开(公告)日：2003-05-20

申请号：US09525472

申请日：2000-03-15

Applicant: Srinivasa S. N. Reddy ,  Donald R. Wall

Inventor： Srinivasa S. N. Reddy ,  Donald R. Wall

IPC: B05D512

CPC classification number: H05K3/246 ,  C04B41/009 ,  C04B41/52 ,  C04B41/89 ,  C04B2111/00844 ,  H01L23/49883 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/245 ,  H05K3/4061 ,  H05K2201/0317 ,  H05K2201/0347 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/265 ,  C04B41/4539 ,  C04B41/4572 ,  C04B41/5031 ,  C04B41/5041 ,  C04B41/5042 ,  C04B41/5144 ,  C04B35/00 ,  H01L2924/00

Abstract: A paste for one of a via and an external feature, such as a pad, tab, or line, of a ceramic substrate, includes at least one of titania and zirconia, and a filler material mixed with the at least one of titania and zirconia. Further, the via structure or external feature such as an input/output pad, tab, or line, includes a metallic plating thereover. A method of forming the via structure or the external feature on the ceramic substrate, includes steps of either depositing the paste in the via of the ceramic substrate or depositing the paste on the ceramic substrate, and depositing, by a dry process metallic plating, a metallic plating on the paste. The paste includes at least one of titania and zirconia for reducing residual stress without effecting the platability of the metallic plating.

Abstract translation: 用于陶瓷基板的通孔和外部特征（例如垫，突片或线）之一的糊料包括二氧化钛和氧化锆中的至少一种，以及与二氧化钛和氧化锆中的至少一种混合的填充材料 。 此外，通孔结构或诸如输入/输出焊盘，突片或线的外部特征包括其上的金属电镀。 在陶瓷基板上形成通孔结构或外部特征的方法包括以下步骤：将糊料沉积在陶瓷基板的通孔中或将该糊料沉积在陶瓷基板上，并通过干法金属镀层沉积 金属电镀在糊状物上。 糊料包括二氧化钛和氧化锆中的至少一种，用于降低残余应力而不影响金属镀层的镀层。

公开(公告)号：US06535012B1

公开(公告)日：2003-03-18

申请号：US09568707

申请日：2000-05-11

Applicant: Alan G. Wood ,  Tim J. Corbett

Inventor： Alan G. Wood ,  Tim J. Corbett

IPC: G01R3128

CPC classification number: H01L24/80 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/0491 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2855 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/20 ,  H01L22/22 ,  H01L23/13 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract translation: 用于测试半导体晶片上的无引脚骰子的可重复使用的老化/测试夹具由两半组成。 测试夹具的前半部分是用于接收晶片的晶片腔板，第二半部分在晶片和电气测试设备之间建立电气连通。 刚性基板在其上具有与晶片电接触的导体。 在老化和电气测试完成之前，测试夹具不需要打开。 在老化应力和电气测试之后，可以将单个裸片或单独的封装裸片与封装裸片之间建立互为独立部件，阵列或簇的互连，或者作为单个部分或阵列。

公开(公告)号：US20030022419A1

公开(公告)日：2003-01-30

申请号：US09939480

申请日：2001-08-24

Inventor： Shih-Ping Hsu

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/113 ,  H05K3/0094 ,  H05K3/3473 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Disclosed is a method for fabricating vias in solder pads of a ball grid array (BGA) substrate. The substrate is drilled to form the plural vias, and then the interior surfaces of said vias are plated with a copper layer for forming the electrically conductive vias. After the high solid content of the resin is adopted for being plugged into the electrically conductive vias, the both ends of the electrically conductive vias and the upper surface and the lower surface of the substrate are plated with a copper layer. Then said copper layers are etched to form the upper circuit layer and the lower circuit layer and the solder pads. The method in present invention can increase the density of the circuits. Because the both ends of the electrically conductive vias plugged with the resin are very planar, it can be made use of forming a core layer for the built-up fabrication.

公开(公告)号：US20020189094A1

公开(公告)日：2002-12-19

申请号：US10225862

申请日：2002-08-22

Applicant: International Business Machines Corporation

Inventor： Thomas R. Miller ,  William J. Rudik ,  Robert J. Testa ,  Kevin P. Unger ,  Michael Wozniak

IPC: H05K003/02 ,  H05K003/46

CPC classification number: H05K3/4623 ,  H01L23/49822 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K3/246 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2203/0554 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, disclosed is the provision of a method for producing an impedance controlled printed circuit wiring board. Also, there is the provision of a method for producing high speed printed wiring boards with multiple differential impedance controlled layers.

公开(公告)号：US20020175438A1

公开(公告)日：2002-11-28

申请号：US10191378

申请日：2002-07-08

Applicant: International Business Machines Corporation

Inventor： Peter A. Gruber ,  Frederic Maurer ,  Lubomyr Taras Romankiw

IPC: B29C045/14 ,  B29C045/63

CPC classification number: H05K3/4069 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4602 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0126 ,  H05K2203/085 ,  H01L2924/00

Abstract: An apparatus and a method for filling high aspect ratio holes in electronic substrates that can be advantageously used for filling holes having aspect ratios larger than 5:1 are disclosed. In the apparatus, a filler plate and a vacuum plate are used in conjunction with a connection means such that a gap is formed between the two plates to accommodate an electronic substrate equipped with high aspect ratio via holes. The filler plate is equipped with an injection slot while the vacuum plate is equipped with a vacuum slot such that when a substrate is sandwiched therein, via holes can be evacuated of air and injected with a liquid simultaneously from a bottom side and a top side of the substrate. The present invention novel apparatus and method allows the filling of via holes that have small diameters, i.e., as small as 10 nullm, and high aspect ratios, i.e., at least 5:1 to be filled with an electrically conductive material such as a solder or a conductive polymer such that vias or interconnects can be formed in electronic substrates. The present invention apparatus and method can be advantageously used in fabricating substrates for display panels by forming conductive vias and interconnects for placing a voltage potential on pixel display elements formed on the display panels.

Abstract translation: 公开了一种用于填充电子基板中的高纵横比孔的装置和方法，其可以有利地用于填充具有大于5:1的纵横比的孔。 在装置中，填充板和真空板与连接装置结合使用，使得在两个板之间形成间隙以容纳配备有高纵横比通孔的电子基板。 填充板配备有注入槽，而真空板配备有真空槽，使得当基板夹在其中时，通孔可以从空气排出并同时从液体的底侧和顶侧注入液体 底物。 本发明的新型装置和方法允许填充具有小直径，即小至10um，高纵横比，即至少5:1的通孔，以填充诸如焊料的导电材料 或导电聚合物，使得可以在电子基板中形成通孔或互连。 本发明的装置和方法可以有利地用于制造用于显示面板的基板，通过形成用于在形成在显示面板上的像素显示元件上放置电压电位的导电通孔和互连。