公开(公告)号：US4521476A

公开(公告)日：1985-06-04

申请号：US506589

申请日：1983-06-22

Applicant: Shinichiro Asai ,  Kazuo Katoh ,  Tatsuo Nakano

Inventor： Shinichiro Asai ,  Kazuo Katoh ,  Tatsuo Nakano

IPC: H05K3/06 ,  H01L21/48 ,  H01L21/60 ,  H01L23/14 ,  H01L25/16 ,  H05K1/09 ,  H05K3/24 ,  B32B3/00 ,  H01L27/10

CPC classification number: H01L24/85 ,  H01L21/4846 ,  H01L23/142 ,  H01L25/16 ,  H05K1/09 ,  H05K3/243 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2201/2081 ,  H05K2203/0361 ,  H05K2203/049 ,  H05K3/06 ,  Y10S428/901 ,  Y10T428/12438 ,  Y10T428/1275 ,  Y10T428/12903 ,  Y10T428/24917

Abstract: A hybrid integrated circuit is prepared by laminating an aluminum-copper clad foil on an insulating layer, etching the aluminum-copper clad foil with etching agents to form an aluminum circuit and a copper circuit and connecting a semiconductor element to the aluminum circuit through an aluminum wire or a gold wire while connecting a circuit element to the copper circuit by soldering.

Abstract translation: 混合集成电路是通过在绝缘层上层叠铝 - 铜包覆箔，用蚀刻剂蚀刻铝 - 铜包覆箔以形成铝电路和铜电路并通过铝连接半导体元件到铝电路 电线或金线，通过焊接将电路元件连接到铜电路。

公开(公告)号：US12101880B2

公开(公告)日：2024-09-24

申请号：US17688219

申请日：2022-03-07

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Hee-Joon Chun ,  Jae Sung Sim ,  Hak Young Lee ,  Kwang Hee Kwon ,  Hee Jung Jung

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/092 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/422 ,  H05K3/423 ,  H05K3/429 ,  H05K2201/0391 ,  H05K2201/09563 ,  H05K2203/025

Abstract: A printed circuit board includes: a first insulating layer; a first metal layer disposed on one surface of the first insulating layer; a second metal layer disposed on the other surface facing the one surface of the first insulating layer; a via penetrating through the first insulating layer to connect the first and second metal layers to each other; and a heterogeneous metal region disposed in at least one of an area in which the via is adjacent to the first insulating layer and an area in which the via is adjacent to the first metal layer, and including a material different from that of the via, wherein the heterogeneous metal region includes at least one of nickel (Ni), silicon (Si), and titanium (Ti).

公开(公告)号：US20240284591A1

公开(公告)日：2024-08-22

申请号：US18650918

申请日：2024-04-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tsuyoshi TAKAKURA ,  Masaaki MIZUSHIRO ,  Satoshi IZUMI ,  Ryuichiro WADA ,  Hiroki YOSHIMORI ,  Yoshihito OTSUBO ,  Tadashi NOMURA

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0367 ,  H05K2201/0391

Abstract: A circuit module includes: a substrate including a first main surface and a second main surface; a resin layer on the first main surface of the substrate; an electronic component; a penetrating portion penetrating the resin layer in a thickness direction; a first conductor that is a pillar conductor present in the penetrating portion, the first conductor including a first bottom closer to the substrate and a second bottom inward of an outer surface of the resin layer; a second conductor that is a metal film covering at least a portion of a side surface of the first conductor, the second conductor including a portion extending continuously from the side surface of the first conductor to the same plane with the outer surface of the resin layer.

公开(公告)号：US11862518B2

公开(公告)日：2024-01-02

申请号：US16914900

申请日：2020-06-29

Applicant: Analog Devices International Unlimited Company

Inventor： Jan Kubik ,  Bernard P. Stenson ,  Michael Noel Morrissey

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/288 ,  H01L21/033 ,  C23C18/16 ,  H01L23/532 ,  C25D5/02 ,  C25D7/12 ,  C25D5/10 ,  H05K3/24 ,  H05K3/18 ,  H05K3/42 ,  H01L49/02 ,  H05K1/02

CPC classification number: H01L21/76885 ,  C23C18/1605 ,  C23C18/1651 ,  C25D5/022 ,  C25D5/10 ,  C25D7/123 ,  H01L21/0331 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L28/10 ,  H05K3/184 ,  H05K3/244 ,  H05K3/422 ,  H05K1/0265 ,  H05K3/188 ,  H05K3/424 ,  H05K2201/0367 ,  H05K2201/0391 ,  H05K2201/096 ,  H05K2201/09563 ,  H05K2201/09845 ,  H05K2203/0716 ,  H05K2203/1407 ,  H05K2203/1423 ,  H05K2203/1476

Abstract: The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

公开(公告)号：US20180103548A1

公开(公告)日：2018-04-12

申请号：US15839464

申请日：2017-12-12

Applicant: International Business Machines Corporation

Inventor： Brian L. Carlson ,  John R. Dangler ,  Roger S. Krabbenhoft ,  Kevin A. Splittstoesser

IPC: H05K3/26 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46 ,  H01P3/02 ,  H05K3/38 ,  H05K1/02 ,  H05K3/06 ,  H05K1/09 ,  H05K1/03

CPC classification number: H05K3/26 ,  H01P3/02 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0242 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K3/06 ,  H05K3/064 ,  H05K3/382 ,  H05K3/46 ,  H05K3/4611 ,  H05K2201/0355 ,  H05K2201/0391 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A circuit apparatus includes at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.

公开(公告)号：US09812412B2

公开(公告)日：2017-11-07

申请号：US14980404

申请日：2015-12-28

Applicant: ROHM CO., LTD.

Inventor： Takuma Shimoichi ,  Yasuhiro Kondo

IPC: H01L23/66 ,  H01L49/02 ,  H01L27/01

CPC classification number: H01L23/66 ,  H01L27/016 ,  H01L28/10 ,  H01L28/20 ,  H01L28/60 ,  H01L2223/6672 ,  H01L2924/0002 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/107 ,  H05K3/146 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0376 ,  H05K2201/0391 ,  H05K2201/09263 ,  H05K2201/09981 ,  H05K2201/10181 ,  H05K2203/0353 ,  H05K2203/1338 ,  H01L2924/00

Abstract: A chip part includes a substrate, a first electrode and a second electrode which are formed apart from each other on the substrate and a circuit network which is formed between the first electrode and the second electrode. The circuit network includes a first passive element including a first conductive member embedded in a first trench formed in the substrate and a second passive element including a second conductive member formed on the substrate outside the first trench.

公开(公告)号：US09807848B2

公开(公告)日：2017-10-31

申请号：US14792092

申请日：2015-07-06

Applicant: YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY OF JERUSALEM, LTD.

Inventor： Shlomo Magdassi ,  Michael Grouchko ,  Michael Layani

IPC: H05B33/28 ,  H01B1/02 ,  H01B1/10 ,  H01L31/0224 ,  C23C4/18 ,  C23C26/00 ,  H01L31/18 ,  H05K1/03 ,  H05K1/09 ,  H05K3/12 ,  C23C16/513 ,  B05D3/10 ,  B05D5/06 ,  B05D5/12 ,  H01L33/42 ,  H05K1/02 ,  H05K3/14

CPC classification number: H05B33/28 ,  B05D3/107 ,  B05D5/061 ,  B05D5/12 ,  C23C4/18 ,  C23C16/513 ,  C23C26/00 ,  H01B1/02 ,  H01B1/026 ,  H01B1/10 ,  H01L31/022466 ,  H01L31/1884 ,  H01L33/42 ,  H01L2924/0002 ,  H01L2933/0016 ,  H05K1/0225 ,  H05K1/0278 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/0386 ,  H05K1/0393 ,  H05K1/092 ,  H05K1/095 ,  H05K1/097 ,  H05K3/125 ,  H05K3/14 ,  H05K2201/0257 ,  H05K2201/026 ,  H05K2201/0302 ,  H05K2201/0323 ,  H05K2201/0329 ,  H05K2201/0338 ,  H05K2201/035 ,  H05K2201/0391 ,  H05K2201/0969 ,  H05K2201/10053 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2203/0545 ,  H05K2203/1173 ,  H05K2203/125 ,  Y02E10/50 ,  Y10T428/24273 ,  Y10T428/24331 ,  Y10T428/249978 ,  Y10T428/249979 ,  H01L2924/00

Abstract: The invention provides processes for the manufacture of conductive transparent films and electronic or optoelectronic devices comprising same.

公开(公告)号：US09735133B2

公开(公告)日：2017-08-15

申请号：US15290232

申请日：2016-10-11

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Makoto Agatani ,  Toshio Hata ,  Tomokazu Nada ,  Shinya Ishizaki

IPC: H01L33/62 ,  H01L25/075 ,  F21K9/00 ,  H05K1/11 ,  F21V23/06 ,  H01L33/54 ,  H01L33/48 ,  H01L33/52 ,  F21Y101/00 ,  F21Y105/10 ,  F21K9/232 ,  F21Y115/10

CPC classification number: H01L25/0753 ,  F21K9/00 ,  F21K9/232 ,  F21V23/06 ,  F21Y2101/00 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L33/483 ,  H01L33/52 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/01327 ,  H01L2933/0066 ,  H05K1/11 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2201/0979 ,  H05K2201/10106 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light-emitting device capable of ensuring an electric connection between a light-emitting element and an electrode without generating any problem in practical use, by both connecting methods with a solder and a connector, and a lighting device provided with the light-emitting device are provided. The light-emitting device according to the present invention has a plurality of LED chips, and a soldering electrode land and a connector connecting electrode land electrically connected to the chips, on a ceramic substrate. The soldering electrode land is formed of a first conductive material having a function to prevent diffusion to a solder, and the connector connecting electrode land is formed of a second conductive material having a function to prevent oxidation.

公开(公告)号：US20170079131A1

公开(公告)日：2017-03-16

申请号：US14855635

申请日：2015-09-16

Applicant: International Business Machines Corporation

Inventor： Brian L. Carlson ,  John R. Dangler ,  Roger S. Krabbenhoft ,  Kevin A. Splittstoesser

IPC: H05K1/02 ,  H05K3/06

CPC classification number: H05K3/26 ,  H01P3/02 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0242 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K3/06 ,  H05K3/064 ,  H05K3/382 ,  H05K3/46 ,  H05K3/4611 ,  H05K2201/0355 ,  H05K2201/0391 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A circuit apparatuses include at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.

Abstract translation: 电路装置包括由图案化导电片形成的至少一个电路特征。 导电片包括不规则表面和平坦化表面。 电路装置的第一区域的导电片粗糙度最小化，并保持在电路装置的第二区域。 选择性地平坦化导电片的部分允许利用较低成本的较粗糙的导电片。 平坦化表面允许增加的信号完整性和降低的插入损耗，并且不规则表面允许增加电路装置的粘附性和增强可靠性。

公开(公告)号：US20160366766A1

公开(公告)日：2016-12-15

申请号：US14886581

申请日：2015-10-19

Applicant: HongQiSheng Precision Electronics (QinHuangDao) Co.,Ltd. ,  FuKui Precision Component (Shenzhen) Co., Ltd. ,  Zhen Ding Technology Co., Ltd.

Inventor： TZU-CHIEN YEH

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/40 ,  H05K1/03 ,  H05K3/18 ,  H05K3/46 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K1/184 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/092 ,  H05K1/111 ,  H05K1/115 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/0203 ,  H05K2201/0391 ,  H05K2201/09545 ,  H05K2203/0278 ,  H05K2203/122 ,  H05K2203/1536 ,  Y10T29/49165

Abstract: A circuit board includes a core layer, at least one passive component, a first and a second conductive wire layers, at least one contact pad, and a resin packing layer. The core layer defines at least one through hole to receive the passive component. The first and the second conductive wire layers are connected to two opposite surfaces of the core layer. Each contact pad is positioned between and connected to one passive component and the first conductive wire layer. The resin packing layer is filled among the core layer, each passive component, each contact pad, the first and the second conductive wire layers. The resin packing layer can connect the first and the second conductive wire layers to the core layer, and connect the core layer, each passive component, and each contact pads to each other.

Abstract translation: 电路板包括芯层，至少一个无源部件，第一和第二导线层，至少一个接触焊盘和树脂封装层。 芯层限定至少一个通孔以接收无源部件。 第一和第二导线层连接到芯层的两个相对的表面。 每个接触垫位于一个无源部件和第一导电层之间并连接到其上。 在芯层，每个无源部件，每个接触焊盘，第一和第二导线层中填充树脂填充层。 树脂填充层可以将第一和第二导线层连接到芯层，并且将芯层，每个无源部件和每个接触焊盘彼此连接。