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    CIRCUIT DESIGN ASSEMBLIES
    113.
    发明申请
    CIRCUIT DESIGN ASSEMBLIES 审中-公开
    电路设计组件

    公开(公告)号：US20110008974A1

    公开(公告)日：2011-01-13

    申请号：US12501408

    申请日：2009-07-11

    Applicant: IOAN ALEXANDRU SALOMIE

    Inventor： IOAN ALEXANDRU SALOMIE

    IPC: H01R12/00 ,  G06F17/50 ,  H05K3/00

    CPC classification number: H01R9/28 ,  G06F17/5068 ,  G06F2217/40 ,  H05K1/0286 ,  H05K3/103 ,  H05K3/222 ,  H05K3/4046 ,  H05K2201/09609 ,  H05K2201/09963 ,  H05K2201/1028 ,  H05K2201/10333 ,  H05K2201/1059 ,  Y10T29/49124

    Abstract: Circuit design assemblies, referred to herein as a “SpinBoard” and “SpinConnector” assemblies, are disclosed. The assemblies may include any of a variety of advantageous structures, including for example a board with a grid defining circuit point positions, and SpinConnector structures for building circuits. The disclosed SpinConnector structures may include advantageous features such as pin and plate structures that allow building fixed or articulating connector chains, and improved contact structures for conductive contact with electronic components. Software for designing the provided assemblies is also disclosed.

    Abstract translation: 公开了电路设计组件，这里称为“SpinBoard”和“SpinConnector”组件。 组件可以包括各种有利的结构中的任何一种，包括例如具有限定电路点位置的网格的板以及用于构建电路的SpinConnector结构。 所公开的旋转连接器结构可以包括有利特征，例如能够构建固定或铰接连接器链的销和板结构，以及用于与电子部件的导电接触的改进的接触结构。 还公开了用于设计所提供的组件的软件。

    Ground straddling in PTH pinfield for improved impedance
    115.
    发明授权
    Ground straddling in PTH pinfield for improved impedance 有权
    地面跨越PTH引脚，以改善阻抗

    公开(公告)号：US07830223B2

    公开(公告)日：2010-11-09

    申请号：US12107970

    申请日：2008-04-23

    Applicant: Bilal Ahmad

    Inventor： Bilal Ahmad

    IPC: H03H7/38

    CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/0253 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09609 ,  H05K2201/09718 ,  H05K2201/10189 ,  Y10T29/49155

    Abstract: High-speed communication links are improved by having differential pairs of traces in a connector pinfield on layers of a multilayer printed circuit board (PCB) to straddle respective rows of reference (ground) pins rather than the respective rows of signal vias. Thus, a desirable increase in the size of each an anti-pad to surrounding each signal via pad can be incorporated without forcing tracing of adjacent differential pairs closer to one another, and thus increased cross talk is avoided. Thereby, 50 ohm or close to 50 ohm impedance for each signal via is achieved. Spacing and routing between traces of each differential pair are advantageously adjusted for skew compensation and impedance optimization utilizing three dimensional computational electromagnetic tools.

    Abstract translation: 通过在多层印刷电路板（PCB）的多层印刷电路板（PCB）上的连接器引脚区域中的差分对迹线来跨越相应行的参考（接地）引脚而不是相应的信号通孔行来提高高速通信链路。 因此，可以并入每个反焊盘的大小对于围绕每个信号通过焊盘的期望的增加，而不强制相邻的差分对的跟踪彼此靠近，从而避免了增加的串扰。 因此，实现了每个信号通孔的50欧姆或接近50欧姆的阻抗。 有利地利用三维计算电磁工具对每个差分对的迹线之间的间距和布线进行偏斜补偿和阻抗优化。

    PRINTED WIRING BOARD
    116.
    发明申请
    PRINTED WIRING BOARD 失效
    印刷线路板

    公开(公告)号：US20090294166A1

    公开(公告)日：2009-12-03

    申请号：US12390168

    申请日：2009-02-20

    Applicant: Hideaki YOSHIMURA ,  Kenji IIDA ,  Tomoyuki ABE ,  Yasutomo MAEHARA ,  Shin HIRANO

    Inventor： Hideaki YOSHIMURA ,  Kenji IIDA ,  Tomoyuki ABE ,  Yasutomo MAEHARA ,  Shin HIRANO

    IPC: H05K1/11

    CPC classification number: H05K3/445 ,  H05K3/4608 ,  H05K2201/0323 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09809

    Abstract: Large-sized through holes are formed in a core layer of a printed wiring board. Large-sized vias are formed in the shape of a cylinder along the inward wall surfaces of the large-sized through holes located within a specific area. A filling material fills the inner space of the large-sized via. A small-sized through hole penetrates through the corresponding filling material along the longitudinal axis of the small-sized through hole. A small-sized via is formed in the shape of a cylinder along the inward wall surface of the small-sized through hole. The filling material and the core layer are uniformly distributed within the specific area in the in-plane direction of the core substrate. This results in suppression of uneven distribution of thermal stress in the core layer in the in-plane direction of the core layer.

    Abstract translation: 在印刷电路板的芯层中形成大尺寸的通孔。 大尺寸通孔沿着位于特定区域内的大尺寸通孔的内壁表面形成为圆柱体的形状。 填充材料填充大尺寸通孔的内部空间。 小尺寸的通孔穿过相应的填充材料沿着小尺寸通孔的纵向轴线。 小尺寸的通孔沿着小尺寸通孔的内壁表面形成为圆柱体的形状。 填充材料和芯层均匀地分布在芯基板的面内方向的特定区域内。 这导致抑制芯层在芯层的面内方向上的热应力的不均匀分布。

    High-frequency electromagnetic bandgap device and method for making same
    117.
    发明授权
    High-frequency electromagnetic bandgap device and method for making same 有权
    高频电磁带隙装置及其制造方法

    公开(公告)号：US07586444B2

    公开(公告)日：2009-09-08

    申请号：US11633769

    申请日：2006-12-05

    Applicant: Carl W. Berlin ,  Deepukumar M. Nair

    Inventor： Carl W. Berlin ,  Deepukumar M. Nair

    IPC: H01Q1/38 ,  H01Q15/02

    CPC classification number: H01Q15/0026 ,  H01P1/2005 ,  H01Q15/006 ,  H05K1/0216 ,  H05K2201/09309 ,  H05K2201/09609 ,  Y10T29/49016

    Abstract: A high-frequency Electromagnetic Bandgap (EBG) device, and a method for making the device are provided. The device includes a first substrate including multiple conducting vias forming a periodic lattice. The vias of the first substrate extend from the lower surface of the first substrate to the upper surface of the first substrate. The device also includes a second substrate having multiple conducting vias forming a periodic lattice. The vias of the second substrate extend from the lower surface of the second substrate to the upper surface of the second substrate. The second substrate is positioned adjacent to, and overlapping, the first substrate, such that the lower surface of the second substrate is in contact with the upper surface of the first substrate, and such that a plurality of vias of the second substrate are in contact with a corresponding plurality of vias of the first substrate.

    Abstract translation: 提供高频电磁带隙（EBG）装置及其制造方法。 该器件包括包括形成周期性晶格的多个导电通孔的第一衬底。 第一衬底的通孔从第一衬底的下表面延伸到第一衬底的上表面。 该器件还包括具有形成周期性晶格的多个导电通孔的第二衬底。 第二基板的通孔从第二基板的下表面延伸到第二基板的上表面。 第二基板定位成与第一基板相邻并重叠，使得第二基板的下表面与第一基板的上表面接触，并且使得第二基板的多个通孔接触 与第一基板的对应的多个通孔。

    GROUND STRADDLING IN PTH PINFIELD FOR IMPROVED IMPEDANCE
    118.
    发明申请
    GROUND STRADDLING IN PTH PINFIELD FOR IMPROVED IMPEDANCE 有权
    用于改善阻抗的PTH引脚的接地拉伸

    公开(公告)号：US20090188711A1

    公开(公告)日：2009-07-30

    申请号：US12107970

    申请日：2008-04-23

    Applicant: Bilal Ahmad

    Inventor： Bilal Ahmad

    IPC: H05K1/11 ,  H05K3/10

    CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/0253 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09609 ,  H05K2201/09718 ,  H05K2201/10189 ,  Y10T29/49155

    Abstract: High-speed communication links are improved by having differential pairs of traces in a connector pinfield on layers of a multilayer printed circuit board (PCB) to straddle respective rows of reference (ground) pins rather than the respective rows of signal vias. Thus, a desirable increase in the size of each an anti-pad to surrounding each signal via pad can be incorporated without forcing tracing of adjacent differential pairs closer to one another, and thus increased cross talk is avoided. Thereby, 50 ohm or close to 50 ohm impedance for each signal via is achieved. Spacing and routing between traces of each differential pair are advantageously adjusted for skew compensation and impedance optimization utilizing three dimensional computational electromagnetic tools.

    Abstract translation: 通过在多层印刷电路板（PCB）的多层印刷电路板（PCB）上的连接器引脚区域中的差分对迹线来跨越相应行的参考（接地）引脚而不是相应的信号通孔行来提高高速通信链路。 因此，可以并入每个反焊盘的大小对于围绕每个信号通过焊盘的期望的增加，而不强制相邻的差分对的跟踪彼此靠近，从而避免了增加的串扰。 因此，实现了每个信号通孔的50欧姆或接近50欧姆的阻抗。 有利地利用三维计算电磁工具对每个差分对的迹线之间的间距和布线进行偏斜补偿和阻抗优化。

    CIRCUIT BOARD AND RADIATING HEAT SYSTEM FOR CIRCUIT BOARD
    119.
    发明申请
    CIRCUIT BOARD AND RADIATING HEAT SYSTEM FOR CIRCUIT BOARD 失效
    电路板电路板和放电加热系统

    公开(公告)号：US20090038826A1

    公开(公告)日：2009-02-12

    申请号：US12162740

    申请日：2007-02-07

    Applicant: Ki-Geon Lee

    Inventor： Ki-Geon Lee

    IPC: H05K7/20 ,  H05K1/11 ,  H05K1/16

    CPC classification number: H05K1/0206 ,  H05K1/116 ,  H05K3/0061 ,  H05K3/3447 ,  H05K3/42 ,  H05K2201/09609 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10106 ,  H05K2201/10303 ,  H05K2201/10651

    Abstract: A circuit board and a heat radiating system of the circuit board. In the circuit board, a plurality of conductive layer regions coated with a conductor are separately formed on both sides of an insulating substrate, the conductive layer region formed on either side of an insulating region on each of the both sides of the insulating substrate, the plurality of the conductive layer regions includes a plurality of through holes which penetrate through the insulating substrate and are coated with a conductor over an inner wall, the conductor in the through hole electrically conducts the coated conductor of the plurality of the conductive layer regions, one of the lead pins is connected to one of the separated conductive layer regions on the both sides based on the insulating region, and the other lead pin is connected to the other conductive layer region. Accordingly, the efficient heat radiation of the circuit board can prevent the component malfunction, the lifespan reduction, the power consumption increase, and the illuminance drop.

    Abstract translation: 电路板的电路板和散热系统。 在电路基板中，在绝缘基板的两面分别形成涂布有导体的多个导电层区域，在绝缘基板的两侧的绝缘区域的两侧形成的导电层区域， 多个导电层区域包括穿过绝缘基板并在内壁上涂覆有导体的多个通孔，通孔中的导体导电多个导电层区域的涂覆导体，一个 基于绝缘区域将引线引脚连接到两侧的分离的导电层区域中的一个，另一个引脚与另一个导电层区域连接。 因此，电路板的高效散热可以防止元件故障，寿命降低，功率消耗增加和照度下降。

    High impedance electromagnetic surface and method
    120.
    发明授权
    High impedance electromagnetic surface and method 失效
    高阻抗电磁表面和方法

    公开(公告)号：US07423608B2

    公开(公告)日：2008-09-09

    申请号：US11312286

    申请日：2005-12-20

    Applicant: Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

    Inventor： Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

    IPC: H01Q15/24

    CPC classification number: H01Q15/006 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09609

    Abstract: A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates, wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).

    Abstract translation: 高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319） 电路板（302）。 多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。 每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。 电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器 在印刷电路板（302）内。

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