公开(公告)号：US20020017721A1

公开(公告)日：2002-02-14

申请号：US09756086

申请日：2001-01-08

Inventor： Chien-Ping Huang

IPC: H01L023/34

CPC classification number: H01L21/4853 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10477 ,  H05K2201/10992 ,  H05K2201/2036 ,  H05K2203/041 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A solder ball array type package structure is able to control collapse. The package includes a substrate, a carrier, a plurality of dies, a molding compound and a plurality of solder balls. The substrate has at least one active surface. Pads are located on the first surface of the substrate. The carrier has at least an active surface and a back surface opposite the active surface. A plurality of dies are located on the back surface and the active surface of the carrier. The dies arranged on the active surface are electrically connected to the carrier by flip chip technology. A molding compound encapsulates on the back surface of the carrier to cover the dies on the back surface of the carrier. Solder balls having a base material are provided on the active surface of the carrier in array. At least three solder balls coated with the base material having a high melting-temperature core are further provided in the periphery of the array. The carrier is arranged such that the active surface faces the first surface of the substrate to allow each solder ball correspond to the one of the pads, respectively.

Abstract translation: 焊球阵列式封装结构能够控制崩溃。 该封装包括基板，载体，多个模具，模塑料和多个焊球。 衬底具有至少一个活性表面。 垫片位于基板的第一表面上。 载体至少具有与活性表面相对的活性表面和后表面。 多个模具位于载体的背面和活性表面上。 布置在有源表面上的管芯通过倒装芯片技术与载体电连接。 模塑料封装在载体的背面，以覆盖载体背面上的模具。 具有基材的焊球被设置在载体的有源表面上。 在阵列的周围还设有至​​少三个涂覆有具有高熔点芯的基材的焊球。 载体布置成使得活性表面面向基板的第一表面，以允许每个焊球分别对应于焊盘之一。

公开(公告)号：US06344695B1

公开(公告)日：2002-02-05

申请号：US09414503

申请日：1999-10-08

Applicant: Kei Murayama

Inventor： Kei Murayama

IPC: H01L2348

CPC classification number: H05K3/3436 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/10992 ,  H05K2203/043 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor chip has an active surface with electrodes thereon and an insulating layer covering the active surface and having through holes therein through which corresponding electrodes are exposed. Rewiring circuits are formed on the insulating layer, each having a first terminal end extending through a corresponding through hole and electrically connected to a respective electrode and a second terminal end comprising a conductive pad. Respective inner bumps are formed on the second terminal ends of the rewiring circuits. An insulating film is formed on the rewiring circuits and exposed surfaces of the insulating layer and through holes are formed therein corresponding to the conductive pads and into which respective inner bumps are inserted. A respective outer bump is superimposed on each inner bump in the insulating film and projects beyond an exposed surface of the insulating film remote from the semiconductor chip. In an alternative, inner bumps are omitted and the outer bumps are directly superimposed on the conductive pads in the corresponding through holes. A method of making the semiconductor device provides for superimposing outer bumps either directly on the respective conductive pads in the corresponding through holes, where inner bumps are not employed, or superimposing same on the respective inner bumps after superimposing the inner bumps on the respective conductive pads.

Abstract translation: 半导体芯片具有其上具有电极的活性表面和覆盖有源表面的绝缘层，并且在其中具有通孔，相应的电极通过该孔暴露。 重叠电路形成在绝缘层上，每个具有延伸穿过相应通孔并且电连接到相应电极的第一端部和包括导电焊盘的第二端子。 在再布线电路的第二端部形成有各自的内部凸点。 在再布线电路上形成绝缘膜，绝缘层的露出表面形成有与导电焊盘相对应的通孔，并且插入有各自的内凸块。 相应的外部凸起叠加在绝缘膜的每个内部凸起上，并突出超过远离半导体芯片的绝缘膜的暴露表面。 另一方面，省略了内部凸块，并且外部凸块直接叠加在相应通孔中的导电焊盘上。 制造半导体器件的方法提供了将外部凸块直接叠加在不使用内部凸起的相应通孔中的相应导电焊盘上，或者将内部凸块叠加在各个导电焊盘上之后将其叠加在相应的内部凸起上 。

公开(公告)号：US06319810B1

公开(公告)日：2001-11-20

申请号：US08659356

申请日：1996-06-06

Applicant: Masayuki Ochiai ,  Yasuo Yamagishi ,  Ichiro Yamaguchi ,  Masahiro Yoshikawa ,  Koki Otake ,  Masataka Mizukoshi ,  Yuuji Watanabe

Inventor： Masayuki Ochiai ,  Yasuo Yamagishi ,  Ichiro Yamaguchi ,  Masahiro Yoshikawa ,  Koki Otake ,  Masataka Mizukoshi ,  Yuuji Watanabe

IPC: H01L2144

CPC classification number: H01L24/12 ,  B23K3/0623 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H05K3/3463 ,  H05K3/3478 ,  H05K3/3484 ,  H05K3/3489 ,  H05K2201/10992 ,  H05K2203/0113 ,  H05K2203/016 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/0557 ,  H05K2203/087 ,  H05K2203/1105 ,  H05K2203/1157 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/48

Abstract: Method for forming solder bumps on a first member such as a semiconductor chip having electrode pads formed thereon. A flat plate having holes is prepared and the holes are filled with solder paste by squeezing. The flat plate is then overlapped with the first member with the flat plate above the first plate. The flat plate and the first member are heated to a temperature higher than the melting point of the solder alloy in the solder paste. Therefore, solder bumps having identical sizes and uniform structures can be obtained.

Abstract translation: 在诸如其上形成有电极焊盘的半导体芯片的第一部件上形成焊料凸块的方法。 准备具有孔的平板，并通过挤压填充焊膏。 然后平板与第一构件重叠，平板在第一板上。 平板和第一构件被加热到高于焊膏中的焊料合金的熔点的温度。 因此，可以获得具有相同尺寸和均匀结构的焊料凸块。

公开(公告)号：US06310301B1

公开(公告)日：2001-10-30

申请号：US09288749

申请日：1999-04-08

Applicant: Randy T. Heinrich ,  Robert J. Roessler ,  Thang D. Truong ,  Matthew A. Wilkowski ,  William L. Woods, Jr.

Inventor： Randy T. Heinrich ,  Robert J. Roessler ,  Thang D. Truong ,  Matthew A. Wilkowski ,  William L. Woods, Jr.

IPC: H05K116

CPC classification number: H05K3/368 ,  H05K1/141 ,  H05K1/165 ,  H05K3/3436 ,  H05K2201/10234 ,  H05K2201/10257 ,  H05K2201/10666 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0455 ,  Y02P70/613

Abstract: An inter-substrate conductive mount for a surface mountable circuit board, a method of manufacturing the circuit board and a surface mountable power magnetic device. In one embodiment, the circuit board includes: (1) a substrate, (2) an inter-substrate conductive mount composed of a material having a melting point above a solder reflow temperature and including a compliant solder joint at an interface of the substrate and (3) a solder located proximate the conductive mount, the conductive mount of a sufficiently low weight such that a surface tension of a liquid state of the solder is sufficient to maintain the conductive mount in contact with the substrate as the solder is brought to the reflow temperature, the conductive mount being capable of mounting the substrate to an adjacent substrate and providing a conductive path therebetween.

Abstract translation: 一种用于表面安装电路板的基板间导电座，一种制造电路板的方法和一种可表面安装的电力磁性装置。 在一个实施例中，电路板包括：（1）基板，（2）由具有高于焊料回流温度的熔点的材料构成的基板间导电安装件，并且在基板的界面处包括柔性焊接点 （3）位于导电安装座附近的焊料，该导电安装件具有足够低的重量，使得焊料的液体状态的表面张力足以使导电安装座与衬底接触，因为焊料被带到 回流温度，导电安装件能够将衬底安装到相邻的衬底上并且在它们之间提供导电路径。

公开(公告)号：US06300578B1

公开(公告)日：2001-10-09

申请号：US09512131

申请日：2000-02-24

Applicant: Mark Kenneth Hoffmeyer ,  Phillip Duane Isaacs

Inventor： Mark Kenneth Hoffmeyer ,  Phillip Duane Isaacs

IPC: H01R1204

CPC classification number: H05K3/3436 ,  B23K1/0016 ,  B23K2101/42 ,  H05K3/3452 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/09481 ,  H05K2201/09572 ,  H05K2201/10992 ,  H05K2201/2081 ,  H05K2203/043 ,  H05K2203/0455 ,  Y02P70/613

Abstract: Fine pitch area array packaging is achieved using a via-in-pad design within the area array attach portion of a printed circuit board (PCB). The limitation of the design is the wicking action, whereby solder applied to the capture pad contact surface is depleted by capillary action into the via hole when reflowed, causing insufficient solder to be present at the contact surface to effect reliable and repeatable electrical connections. In one implementation, an initial application of solder is applied to plug the via hole with a material having a higher final melting temperature than eutectic solder, thereby providing a stable plug. This plug is formed by the initial solder application that may be either a eutectic solder containing a third metal that forms intermetallic compounds, when reflowed, that elevate the liquidus temperature or a solder having a different formulation with an inherent higher melting temperature. An alternative implementation is to plate the via hole with a material, such as nickel, which prevents eutectic solder, applied to the via capture pad contact surface, from wetting the hole surface and being drawn away from the contact surface by capillary action. Thus, the solder, applied to the via capture pad and used to establish an electrical connection is not depleted.

Abstract translation: 使用在印刷电路板（PCB）的区域阵列附着部分内的通孔焊盘设计实现细间距区域阵列封装。 设计的限制是芯吸作用，由此当回流时，施加到捕获垫接触表面的焊料被毛细管作用通入通孔中，导致在接触表面处存在不足的焊料以实现可靠和可重复的电连接。 在一个实施方案中，施加焊料的初始应用以用比共晶焊料更高的最终熔融温度的材料堵塞通孔，从而提供稳定的插塞。 该插头由初始焊料应用形成，其可以是包含形成金属间化合物的第三金属的共晶焊料，当回流时，提高液相线温度的焊料或具有固有的较高熔融温度的不同配方的焊料。 另一种实施方案是用诸如镍的材料对通孔进行平板化，其防止施加到通孔捕获垫接触表面的共晶焊料润湿孔表面并通过毛细管作用从接触表面拉出。 因此，施加到通孔捕获垫并用于建立电连接的焊料不会耗尽。

公开(公告)号：US20010008778A1

公开(公告)日：2001-07-19

申请号：US09805596

申请日：2001-03-13

Applicant: International Business Machines Corporation

Inventor： Mario J. Interrante ,  Thomas E. Lombardi ,  Frank L. Pompeo ,  William E. Sablinski

IPC: H01L021/44

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  H05K2203/162 ,  H05K2203/176 ,  Y02P70/613 ,  H01L2924/00

Abstract: A temporary attach article of a first component to a second component which includes a first component having a first volume of a fusible material; a second component having a second volume of fusible material; and the first and second components being joined together through the first and second volumes of fusible material, wherein the first volume of fusible material has a melting point higher than a melting point of the second volume of fusible material so that the first and second components may be joined together without melting of the first volume of fusible material and wherein the second volume of fusible material is 5 to 20% of the first volume of fusible material. Also disclosed is a method for temporary attach of devices to an electronic substrate.

Abstract translation: 将第一部件临时附接到第二部件，其包括具有第一容积的可熔材料的第一部件; 具有第二容积的可熔材料的第二部件; 并且所述第一和第二部件通过所述第一和第二体积的可熔材料连接在一起，其中所述第一容积的可熔材料的熔点高于所述第二容积的可熔材料的熔点，使得所述第一和第二部件可以 在不熔化第一体积的可熔材料的情况下连接在一起，并且其中第二体积的可熔材料是第一体积的可熔材料的5至20％。 还公开了一种用于将设备临时附接到电子基板的方法。

公开(公告)号：US06251766B1

公开(公告)日：2001-06-26

申请号：US09388755

申请日：1999-09-02

Applicant: Kishor V. Desai ,  Amit K. Sarkhel

Inventor： Kishor V. Desai ,  Amit K. Sarkhel

IPC: H01L2144

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/041 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Abstract translation: 用于将半导体芯片或球栅阵列模块粘附到支撑基板上的粘合垫包括阶梯形或锥形结构。 该结构由至少一个焊料可湿性金属或其上沉积有焊料的合金层组成。 台阶或锥形结构防止疲劳裂纹在粘合垫上方的X-Y平面中传播。

公开(公告)号：US06235996B1

公开(公告)日：2001-05-22

申请号：US09014804

申请日：1998-01-28

Applicant: Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

Inventor： Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

IPC: H01L2348

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/0272 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent reflows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by a screening mask. Interconnect structures are then bonded to the I/O pad. In a second method, solder preforms in a composition of the transient melting solder paste are wetted onto electronic module I/O pads and interconnect columns or balls are then bonded. Detachment of an electronic module from a circuit card can then be performed by heating the circuit card assembly to a temperature above the eutectic solder melting point, but below the transient solder joint melting point.

Abstract translation: 通过使用包括细金属粉末添加剂的电子模块侧的瞬态焊膏来提供柱和球栅阵列（CGA和BGA）结构的互连结构及其分离方法，以增加熔点 的焊点。 金属粉末添加剂改变焊料接合的组成，使得瞬态熔融焊料组合物在低于+ 230℃的温度下不会完全熔化，并且在随后的回流期间与电子模块分离。 在互连结构的另一端使用具有较低熔点的Pb-Sn共晶体。 在第一种方法中，通过屏蔽掩模将瞬态熔融焊膏施加到电子模块的I / O焊盘。 然后将互连结构结合到I / O焊盘。 在第二种方法中，将瞬态熔融焊膏的组合物中的焊料预成型件润湿到电子模块I / O焊盘上，然后将互连柱或球接合。 然后可以通过将电路卡组件加热到高于共熔焊料熔点但低于瞬态焊点熔点的温度来执行从电路卡分离电子模块。

公开(公告)号：US06199273B1

公开(公告)日：2001-03-13

申请号：US08769449

申请日：1996-12-19

Applicant: Toshihiko Kubo ,  Takuji Ito ,  Hiroshi Takamichi ,  Akihiro Hidaka

Inventor： Toshihiko Kubo ,  Takuji Ito ,  Hiroshi Takamichi ,  Akihiro Hidaka

IPC: H01R900

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L2224/11334 ,  H01L2924/15173 ,  H05K1/113 ,  H05K3/0094 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3478 ,  H05K2201/0379 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/10666 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/074 ,  H05K2203/1394 ,  Y02P70/613 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: A ball-grid array connector structure for an electronic package in which the ball pitch can be reduced to increase the packaging density has a plastic substrate having at least one hollow through-hole and an electrode covering the wall of the through-hole and forming an electrode pad surrounding the through-hole on each surface of the substrate. A metallic ball is joined, either directly or through a solder or a combination of a metallic bump and a solder, to the electrode pad on at least one surface of the substrate at the position of the through-hole. The connector structure can be formed either by sealing an open end of the through-hole on the side to which the ball is not joined, or increasing the pressure within the through-hole by a pressure-control mechanism, before the through-hole is blocked by reflowing the ball itself or the metallic bump or solder used to connect the ball.

Abstract translation: 用于电子封装的球栅阵列连接器结构，其中球节距可以减小以增加封装密度，具有具有至少一个中空通孔的塑料基板和覆盖通孔壁的电极，并形成 围绕基板每个表面上的通孔的电极焊盘。 金属球直接或通过焊料或金属凸块和焊料的组合连接到通孔位置处的基板的至少一个表面上的电极焊盘。 连接器结构可以通过在通孔之前通过密封球体未接合的一侧上的通孔的开口端或通过压力控制机构来增加通孔内的压力来形成 通过回流球本身或用于连接球的金属凸块或焊料来阻止。

公开(公告)号：US06193143B1

公开(公告)日：2001-02-27

申请号：US09366194

申请日：1999-08-04

Applicant: Takatoshi Ishikawa

Inventor： Takatoshi Ishikawa

IPC: B23K3102

CPC classification number: H05K3/3478 ,  H01L21/4846 ,  H01L2224/81 ,  H05K3/3484 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/035 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10992 ,  H05K2203/0195 ,  H05K2203/0338 ,  H05K2203/041 ,  H05K2203/082

Abstract: To present a method and apparatus for forming favorable solder bumps on a substrate of electronic component or the like, in which metal paste is applied on the lower surface of solder balls attracted by a suction tool, and the solder balls are positioned to contact with recesses having the electrode in the bottom, so that the metal paste adhered to the solder balls is adhered to the top of the recesses. Next, the solder balls are moved reciprocally in the vertical direction or horizontal direction. As a result, the metal paste adhered to the top of the recesses is collected to fill up the recesses. Then, the solder balls are put on the top of the recesses, and heated and fused, and solder bumps are formed.

Abstract translation: 为了提出在电子部件等的基板上形成有利的焊料凸块的方法和装置，其中金属浆料被施加在由吸入工具吸引的焊球的下表面上，并且焊球定位成与凹部接触 在底部具有电极，使得粘附到焊球上的金属糊粘附到凹部的顶部。 接下来，焊球在垂直方向或水平方向上往复移动。 结果，收集粘附到凹部顶部的金属糊料以填充凹部。 然后，将焊球放在凹部的顶部，加热熔化，形成焊锡凸块。