公开(公告)号：US20160221823A1

公开(公告)日：2016-08-04

申请号：US15024942

申请日：2014-09-15

Applicant: CAVENDISH KINETICS, INC

Inventor： Mickael RENAULT

IPC: B81C1/00

CPC classification number: B81C1/0038 ,  B81C1/00801 ,  B81C2201/0108 ,  B81C2201/0176 ,  B81C2201/053

Abstract: The present invention generally relates to a method for forming a MEMS device and a MEMS device formed by the method. When forming the MEMS device, sacrificial material is deposited around the switching element within the cavity body. The sacrificial material is eventually removed to free the switching element in the cavity. The switching element has a thin dielectric layer thereover to prevent etchant interaction with the conductive material of the switching element. During fabrication, the dielectric layer is deposited over the sacrificial material. To ensure good adhesion between the dielectric layer and the sacrificial material, a silicon rich silicon oxide layer is deposited onto the sacrificial material before depositing the dielectric layer thereon.

Abstract translation: 本发明一般涉及用于形成MEMS器件的方法和通过该方法形成的MEMS器件。 当形成MEMS器件时，牺牲材料沉积在腔体内的开关元件周围。 牺牲材料最终被去除以释放空腔中的开关元件。 开关元件在其上具有薄的电介质层，以防止蚀刻剂与开关元件的导电材料的相互作用。 在制造期间，介电层沉积在牺牲材料上。 为了确保电介质层和牺牲材料之间的良好粘合性，在沉积其上的电介质层之前，将富硅氧化硅层沉积到牺牲材料上。

公开(公告)号：US20160176703A1

公开(公告)日：2016-06-23

申请号：US14966450

申请日：2015-12-11

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Xavier BAILLIN

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0038 ,  B81B2207/115 ,  B81C1/00285 ,  B81C2201/053 ,  B81C2203/0145 ,  B81C2203/019

Abstract: Getter structure comprising at least: one support; one first layer of getter material arranged on the support; one second layer of getter material such that the first layer of getter material is arranged between the support and the second layer of getter material; one first portion of material mechanically connecting a first face of the second layer of getter material to a first face of the first layer of getter material and forming at least one first space between the first faces of the first and second layers of getter material enabling a circulation of gas between the first faces of the first and second layers of getter material; one first opening crossing through at least the second layer of getter material and emerging into the first space.

Abstract translation: 吸气体结构至少包括：一个支撑件; 第一层吸气材料布置在支架上; 吸气剂材料的第二层，使得第一层吸气材料布置在支撑体和第二层吸气材料之间; 第一部分材料将第二吸气材料层的第一面机械地连接到第一吸气材料层的第一面，并在第一和第二吸气材料层的第一面之间形成至少一个第一空间， 在第一和第二层吸气材料的第一面之间循环气体; 一个第一个开口至少穿过第二层吸气材料，并进入第一个空间。

公开(公告)号：US20160052777A1

公开(公告)日：2016-02-25

申请号：US14930642

申请日：2015-11-02

Applicant: mCube Inc.

Inventor： TE-HSI "TERRENCE" LEE ,  SUDHEER S. SRIDHARAMURTHY ,  SHINGO YONEOKA ,  WENHUA ZHANG

IPC: B81B7/00

CPC classification number: B81B7/0022 ,  B81B3/0086 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2207/11 ,  B81C1/00246 ,  B81C1/0038 ,  B81C1/00531 ,  B81C1/00801 ,  B81C2201/053

Abstract: An integrated circuit includes a substrate member having a surface region and a CMOS IC layer overlying the surface region. The CMOS IC layer has at least one CMOS device. The integrated circuit also includes a bottom isolation layer overlying the CMOS IC layer, a shielding layer overlying a portion of the bottom isolation layer, and a top isolation layer overlying a portion of the bottom isolation layer. The bottom isolation layer includes an isolation region between the top isolation layer and the shielding layer. The integrated circuit also has a MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer. The MEMS layer includes at least one MEMS structure having at least one movable structure and at least one anchored structure. The at least one anchored structure is coupled to a portion of the top isolation layer, and the at least one movable structure overlies the shielding layer.

Abstract translation: 集成电路包括具有表面区域的衬底构件和覆盖在表面区域上的CMOS IC层。 CMOS IC层具有至少一个CMOS器件。 集成电路还包括覆盖CMOS IC层的底部隔离层，覆盖在底部隔离层的一部分上的屏蔽层和覆盖在底部隔离层的一部分上的顶部隔离层。 底部隔离层包括顶部隔离层和屏蔽层之间的隔离区域。 集成电路还具有覆盖顶部隔离层，屏蔽层和底部隔离层的MEMS层。 MEMS层包括具有至少一个可移动结构和至少一个锚定结构的至少一个MEMS结构。 所述至少一个锚定结构耦合到所述顶部隔离层的一部分，并且所述至少一个可移动结构覆盖所述屏蔽层。

公开(公告)号：US09199840B2

公开(公告)日：2015-12-01

申请号：US14069633

申请日：2013-11-01

Applicant: Dubravka Bilic ,  Stephen R. Hooper

Inventor： Dubravka Bilic ,  Stephen R. Hooper

IPC: H01L21/00 ,  G01L9/00 ,  B81C1/00 ,  B81B7/00

CPC classification number: H01L41/0973 ,  B81B7/0035 ,  B81B7/0058 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00825 ,  B81C1/00896 ,  B81C2201/053 ,  B81C2203/0145 ,  H01L41/0926

Abstract: A method of fabricating a sensor device includes forming a plurality of sensor structures on a wafer, covering the plurality of sensor structures with a polymer layer, and dicing the wafer into a plurality of die while each sensor structure remains covered by the polymer layer.

Abstract translation: 制造传感器装置的方法包括在晶片上形成多个传感器结构，用聚合物层覆盖多个传感器结构，并且在每个传感器结构保持被聚合物层覆盖的同时将晶片切割成多个模具。

公开(公告)号：US20150151958A1

公开(公告)日：2015-06-04

申请号：US14411537

申请日：2013-06-29

Applicant: CSM TECHNOLOGIES FAB1 CO., LTD.

Inventor： Dan Dai ,  Xinwei Zhang ,  Guoping Zhou ,  Changfeng Xia

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00825 ,  B81B7/0029 ,  B81C1/0038 ,  B81C2201/0167 ,  B81C2201/053

Abstract: A MEMS chip (100) includes a silicon substrate layer (110), a first oxidation layer (120) and a first thin film layer (130). The silicon substrate layer includes a front surface (112) for a MEMS process and a rear surface (114), both the front surface and the rear surface being polished surfaces. The first oxidation layer is mainly made of silicon dioxide and is formed on the rear surface of the silicon substrate layer. The first thin film layer is mainly made of silicon nitride and is formed on the surface of the first oxidation layer. In the above MEMS chip, by sequentially laminating a first oxidation layer and a first thin film layer on the rear surface of a silicon substrate layer, the rear surface is effectively protected to prevent the scratch damage in the course of a MEMS process. A manufacturing method for the MEMS chip is also provided.

Abstract translation: MEMS芯片（100）包括硅衬底层（110），第一氧化层（120）和第一薄膜层（130）。 硅衬底层包括用于MEMS工艺的前表面（112）和后表面（114），前表面和后表面都是​​抛光表面。 第一氧化层主要由二氧化硅制成，并形成在硅衬底层的后表面上。 第一薄膜层主要由氮化硅制成，并且形成在第一氧化层的表面上。 在上述MEMS芯片中，通过在硅衬底层的后表面依次层叠第一氧化层和第一薄膜层，有效地保护后表面以防止在MEMS工艺过程中的划痕损伤。 还提供了一种用于MEMS芯片的制造方法。

公开(公告)号：US20150028433A1

公开(公告)日：2015-01-29

申请号：US14331285

申请日：2014-07-15

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Xavier BAILLIN ,  Bernard DIEM ,  Jean-Philippe POLIZZI ,  Andre ROUZAUD

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0058 ,  B81B7/0038 ,  B81B7/0077 ,  B81B2201/0228 ,  B81B2207/096 ,  B81C1/00285 ,  B81C1/00301 ,  B81C1/00682 ,  B81C2201/053 ,  B81C2203/0136 ,  B81C2203/0163 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: A structure (100) for encapsulating at least one microdevice (104) produced on and/or in a substrate (102) and positioned in at least one cavity (110) formed between the substrate and a cap (106) rigidly attached to the substrate, in which the cap includes at least: one layer (112) of a first material, one face of which (114) forms an inner wall of the cavity, and mechanical reinforcement portions (116) rigidly attached at least to the said face of the layer of the first material, partly covering the said face of the layer of the first material, and having gas absorption and/or adsorption properties, and in which the Young's modulus of a second material of the mechanical reinforcement portions is higher than that of the first material.

Abstract translation: 一种用于封装至少一个在基板（102）上和/或基板（102）上产生并位于至少一个形成在基板和刚性地附接到基板的盖（106）之间的空腔（110）中的微器件（104）的结构（100） ，其中所述盖至少包括：第一材料的一层（112），其一个面（114）形成所述空腔的内壁，以及至少刚性地附接到所述表面的所述表面的机械加强部分（116） 所述第一材料层，部分覆盖所述第一材料层的所述表面，并且具有气体吸收和/或吸附性能，并且其中所述机械增强部分的第二材料的杨氏模量高于 第一种材料。

公开(公告)号：US20140113412A1

公开(公告)日：2014-04-24

申请号：US14135506

申请日：2013-12-19

Applicant: XINTEC INC.

Inventor： Chia-Lun TSAI ,  Chia-Ming CHENG ,  Long-Sheng YEOU

IPC: H01L21/78

CPC classification number: H01L21/78 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00825 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0118

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

Abstract translation: 本发明的实施例涉及一种芯片封装及其制造方法，其包括芯片保护层或附加的蚀刻停止层，以覆盖导电焊盘，以防止切割残留物损坏或划伤导电焊盘。 根据另一个实施例，当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时，可以使用芯片保护层，其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层， 形成随后的半导体制造工艺的开口。

公开(公告)号：US08637970B2

公开(公告)日：2014-01-28

申请号：US12855447

申请日：2010-08-12

Applicant: Chia-Lun Tsai ,  Chia-Ming Cheng ,  Long-Sheng Yeou

Inventor： Chia-Lun Tsai ,  Chia-Ming Cheng ,  Long-Sheng Yeou

IPC: H01L21/301 ,  H01L21/302

CPC classification number: H01L21/78 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00825 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0118

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

Abstract translation: 本发明的实施例涉及一种芯片封装及其制造方法，其包括芯片保护层或附加的蚀刻停止层，以覆盖导电焊盘，以防止切割残留物损坏或划伤导电焊盘。 根据另一个实施例，当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时，可以使用芯片保护层，其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层， 形成随后的半导体制造工艺的开口。

公开(公告)号：US20120251783A1

公开(公告)日：2012-10-04

申请号：US13432680

申请日：2012-03-28

Applicant: Takeshi SAKAMOTO ,  Junichi TAKEUCHI

Inventor： Takeshi SAKAMOTO ,  Junichi TAKEUCHI

IPC: B32B3/00 ,  B23P17/00

CPC classification number: H01L21/304 ,  B81C1/00063 ,  B81C2201/053

Abstract: A base surface processing method includes forming a protective film on a base surface; thinning a part of a base by grinding a part of the base surface; and etching a ground surface ground by the thinning.

Abstract translation: 基面处理方法包括在基面上形成保护膜; 通过研磨基底表面的一部分来减薄基底的一部分; 并通过变薄来蚀刻地面。

公开(公告)号：US20120134121A1

公开(公告)日：2012-05-31

申请号：US13306493

申请日：2011-11-29

Applicant: Yoko KANEMOTO ,  Ryuji KIHARA

Inventor： Yoko KANEMOTO ,  Ryuji KIHARA

IPC: H05K1/18 ,  H05K3/10 ,  H05K1/16

CPC classification number: B81C1/00801 ,  B81B2201/0271 ,  B81B2207/07 ,  B81C2201/053 ,  Y10T29/49165

Abstract: An electronic device includes: a vibrator disposed within a cavity on a substrate and electrically driven; an enclosure wall which has electric conductivity and sections the cavity from an insulation layer surrounding the circumference of the cavity; a first wiring and a second wiring which connect with the vibrator and penetrate the enclosure wall; and a liquid flow preventing portion disposed at the position where the first wiring and the second wiring penetrate the enclosure wall to prevent flow of etchant dissolving the insulation layer from the cavity toward the insulation layer and insulate the first wiring and the second wiring from the enclosure wall.

Abstract translation: 电子设备包括：振动器，设置在基板上的空腔内并电驱动; 封闭壁，其具有导电性，并且将空腔从围绕空腔圆周的绝缘层分开; 与振动器连接并穿透封闭壁的第一布线和第二布线; 以及设置在所述第一布线和所述第二布线穿过所述封闭壁的位置处的液体流动防止部，以防止将所述绝缘层从所述空腔朝向所述绝缘层溶解的蚀刻剂流动，并且将所述第一布线和所述第二布线与所述封装 壁。