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    Computer system and a computer device
    123.
    发明授权
    Computer system and a computer device 有权

    公开(公告)号：US10002097B2

    公开(公告)日：2018-06-19

    申请号：US15696747

    申请日：2017-09-06

    Applicant: Jonathan Glickman

    Inventor： Jonathan Glickman

    IPC: G06F13/28 ,  G06F13/40 ,  G06F13/16 ,  G06F12/02 ,  G06F13/42

    CPC classification number: G06F13/4027 ,  G06F12/0246 ,  G06F13/1694 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/7201

    Abstract: A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.

    AUTOMATIC MEMORY MANAGEMENT USING A MEMORY MANAGEMENT UNIT
    127.
    发明申请
    AUTOMATIC MEMORY MANAGEMENT USING A MEMORY MANAGEMENT UNIT 审中-公开

    公开(公告)号：US20180137045A1

    公开(公告)日：2018-05-17

    申请号：US15855146

    申请日：2017-12-27

    Applicant: aicas GmbH

    Inventor： Fridtjof Siebert

    IPC: G06F12/02 ,  G06F12/1036

    CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/10 ,  G06F12/1036 ,  G06F2212/7201 ,  G06F2212/7205

    Abstract: In a computer system, an automatic memory management module operates by receiving, from a mutator, memory allocation requests for particular objects to be stored in a random-access memory and allocating particular logical addresses within a logical address space to the particular objects. The automatic memory management module distinguishes the particular objects according to at least one criterion and allocates logical addresses from a first sub-space and logical addresses from a second sub-space. A memory management unit maps the allocated logical addresses from the second sub-space to physical memory in the random-access memory. The logical addresses within the first sub-space are compacted in combination with moving corresponding objects in the random-access memory.

    MEMORY SYSTEM AND METHOD
    129.
    发明申请
    MEMORY SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20180129415A1

    公开(公告)日：2018-05-10

    申请号：US15447916

    申请日：2017-03-02

    Applicant: Toshiba Memory Corporation

    Inventor： Shunichi Igahara ,  Toshikatsu Hida ,  Mitsunori Tadokoro

    IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

    CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/656 ,  G06F2212/7201 ,  G06F2212/7203

    Abstract: According to one embodiment, a memory system includes a nonvolatile first memory, a second memory which has a buffer, and a memory controller. The memory controller manages a plurality of pieces of translation information. In a case where the plurality of pieces of translation information include a first plurality of pieces of translation information, the memory controller caches first translation information among the first plurality of pieces of translation information and does not cache second translation information among the first plurality of pieces of translation information. The first plurality of pieces of translation information linearly correlates a plurality of continuous physical addresses with a plurality of continuous logical addresses.

    MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE
    130.
    发明申请
    MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE 有权

    公开(公告)号：US20180129414A1

    公开(公告)日：2018-05-10

    申请号：US15390547

    申请日：2016-12-26

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Chih-Kang Yeh

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided, wherein the memory storage device includes a rewritable non-volatile memory module and a buffer memory. The method includes: loading at least one first address information of at least one first logical-physical mapping table from the rewritable non-volatile memory module to a first buffer area when the memory storage device is operated in a first mode, wherein the first address information has a first data quantity; and loading at least one second address information of at least one second logical-physical mapping table from the rewritable non-volatile memory module to the first buffer area when the memory storage device is operated in a second mode, wherein the second address information has a second data quantity, and the first data quantity is less than the second data quantity.

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