公开(公告)号：US20070264814A1

公开(公告)日：2007-11-15

申请号：US11737165

申请日：2007-04-19

Applicant: Toshimitsu HIRAI ,  Katsuyuki MORIYA

Inventor： Toshimitsu HIRAI ,  Katsuyuki MORIYA

IPC: H01L21/44

CPC classification number: H01L21/288 ,  H01L21/4867 ,  H01L21/76838 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1292 ,  H01L27/3246 ,  H01L29/41733 ,  H01L51/0022 ,  H05K3/125 ,  H05K3/1258 ,  H05K2201/09254 ,  H05K2201/09727 ,  H05K2201/09909 ,  H05K2203/013 ,  H05K2203/1173 ,  H05K2203/1476

Abstract: A method for forming a metal wiring line, comprises: (a) forming a bank including a first opening corresponding to a first film pattern and a second opening corresponding to a second film pattern that is coupled to the first film pattern and has a width narrower than a width of the first film pattern; (b) disposing a droplet of a functional liquid in the first opening so as to dispose the functional liquid in the second opening by an autonomous flow of the functional liquid; (c) hardening the functional liquid disposed in the first opening and the second opening; and (d) forming the first film pattern and the second film pattern by alternately repeating step (b) and step (c) at least one time.

Abstract translation: 一种用于形成金属布线的方法，包括：（a）形成包括对应于第一膜图案的第一开口和对应于第二膜图案的第二开口的堤，该第二膜图案耦合到第一膜图案并且具有宽度较窄 比第一膜图案的宽度大; （b）在所述第一开口中设置功能液滴，以通过所述功能液体的自主流动将所述功能液体配置在所述第二开口中; （c）硬化设置在第一开口和第二开口中的功能液体; 和（d）至少一次交替地重复步骤（b）和步骤（c）来形成第一膜图案和第二膜图案。

公开(公告)号：US20070109759A1

公开(公告)日：2007-05-17

申请号：US11539706

申请日：2006-10-09

Applicant: Michiharu TORII ,  Kouichi NAGAO ,  Nozomi SHIMOISHIZAKA

Inventor： Michiharu TORII ,  Kouichi NAGAO ,  Nozomi SHIMOISHIZAKA

IPC: H05K7/00

CPC classification number: H05K1/0271 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/09254 ,  H05K2201/09781 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A wiring board includes: a flexible insulating base; a plurality of conductive wirings arranged on the insulating base, end portions of the conductive wirings defining inner leads at a region where a semiconductor chip is to be mounted; and bump electrodes that are provided respectively at the inner leads of the conductive wirings. The wiring board further includes: dummy inner leads having a shape and a pitch corresponding to a shape and a pitch of the inner leads and aligned with the inner leads, the dummy inner leads being provided with dummy bump electrodes corresponding to the bump electrodes; a trunk conductive wiring provided for a group of one or an adjacent plurality of the dummy inner leads; and a branch wiring branching off from the trunk conductive wiring, the branch wiring being connected with the dummy inner leads belonging to the group corresponding to the trunk conductive wiring. Stress concentration on the inner leads during packaging of the semiconductor chip, resulting from the sparse arrangement of the electrode pads of the semiconductor chip, can be alleviated, thus suppressing a break in the inner leads.

Abstract translation: 布线板包括：柔性绝缘基底; 布置在所述绝缘基底上的多个导电布线，所述导电布线的端部在要安装半导体芯片的区域处限定内引线; 以及分别设置在导电布线的内部引线处的凸起电极。 布线板还包括：虚拟内引线，具有与内引线的形状和间距对应的形状和间距，并与内引线对准，虚拟内引线设置有与突起电极对应的虚设凸起电极; 为一组或相邻的多个虚拟内引线设置的躯干导电布线; 以及从所述主干导电布线分支的分支布线，所述分支布线与属于与所述导体布线对应的组的所述虚拟内部引线连接。 可以减轻由半导体芯片的电极焊盘的稀疏布置导致的半导体芯片封装期间的内部引线上的应力集中，从而抑制内部引线的断裂。

公开(公告)号：US20070109709A1

公开(公告)日：2007-05-17

申请号：US10582758

申请日：2004-12-22

Applicant: David Anthony ,  Anthony Anthony ,  William Anthony ,  James Muccioli ,  Richard Neifeld

Inventor： David Anthony ,  Anthony Anthony ,  William Anthony ,  James Muccioli ,  Richard Neifeld

IPC: H02H9/06

CPC classification number: H01G4/35 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/203 ,  H05K1/0233 ,  H05K2201/09254 ,  H05K2201/0969 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/1006 ,  H05K2201/10454 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: An energy conditioner structure comprising a first electrode (120), a second electrode (80), and a shield structure (70, 110, 150) provides improved energy conditioning in electrical circuits. The structures may exist as discrete components or part of an integrated circuit. The shield structure in the energy conditioner structure does not electrically connect to any circuit element.

Abstract translation: 包括第一电极（120），第二电极（80）和屏蔽结构（70,110,150）的能量调节器结构在电路中提供改进的能量调节。 结构可以作为分立组件或集成电路的一部分存在。 能量调节器结构中的屏蔽结构不电连接到任何电路元件。

公开(公告)号：US20070073946A1

公开(公告)日：2007-03-29

申请号：US11473243

申请日：2006-06-23

Applicant: Jean Pierre Conil ,  Victor Cruchet ,  Louis Linares

Inventor： Jean Pierre Conil ,  Victor Cruchet ,  Louis Linares

IPC: G06F13/00

CPC classification number: H05K1/0265 ,  H05K2201/0352 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09727

Abstract: Communication bus having at least one pair of communication lines designed to be connected in series respectively to conductors of a main communication bus designed to be connected to communicating devices of at least one electric panel. Said communication bus comprises at least two branched outputs each having at least two branch lines, said branch lines respectively having a first end connected to a communication line and having a second end designed for connection of the communicating devices. The communication lines are etched on a first conducting layer of a printed circuit, and the branch lines are etched on a second conducting layer of said printed circuit. The communication lines are separated from one another by a distance.

Abstract translation: 通信总线具有至少一对通信线路，其被设计成分别串联连接到设计成连接到至少一个电子面板的通信设备的主通信总线的导体。 所述通信总线包括至少两个分支输出，每个分支输出具有至少两个分支线，所述分支线分别具有连接到通信线路的第一端并且具有设计用于连接通信设备的第二端。 通信线被蚀刻在印刷电路的第一导电层上，并且在所述印刷电路的第二导电层上蚀刻分支线。 通信线路彼此分开一段距离。

公开(公告)号：US20070033490A1

公开(公告)日：2007-02-08

申请号：US11488919

申请日：2006-07-19

Applicant: Karl-Heinz Moosrainer ,  Srdjan Djordjevic ,  Michael Bestele

Inventor： Karl-Heinz Moosrainer ,  Srdjan Djordjevic ,  Michael Bestele

IPC: G11C29/00

CPC classification number: G11C5/025 ,  G06F11/1044 ,  H05K1/181 ,  H05K3/429 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10159 ,  Y02P70/611

Abstract: A semiconductor memory module comprises a control chip for driving ECC memory chips and further memory chips. The memory chips are arranged in two rows on a top side and a bottom side of the module circuit board. The ECC memory chips are arranged centrally on the module circuit board alongside the rows of the memory chips. A control bus connects the ECC memory chips and also the memory chips to the control chip. In a region remote from the control chip, the control bus branches in a contact-making hole into a first partial bus, to which a first group of memory chips are connected, and a second partial bus, to which a second group of memory chips are connected. The ECC memory chips are likewise connected to the control bus via the contact-making hole. Since the ECC memory chips are not arranged directly under the control chip, a bus branch directed backward is not required. As a result, space considerations on the module circuit board are eased and signal integrity on the control buses is improved.

Abstract translation: 半导体存储器模块包括用于驱动ECC存储器芯片和另外的存储器芯片的控制芯片。 存储芯片在模块电路板的上侧和下侧布置成两列。 ECC存储器芯片沿着存储器芯片的行排列在模块电路板的中央。 控制总线将ECC存储器芯片以及存储器芯片连接到控制芯片。 在远离控制芯片的区域中，控制总线将接触孔分支到连接有第一组存储器芯片的第一部分总线和第二部分总线，第二组存储器芯片 被连接。 ECC存储器芯片同样通过接触孔连接到控制总线。 由于ECC存储器芯片不直接布置在控制芯片的下方，所以不需要向后指向的总线分支。 结果，模块电路板上的空间考虑被减轻，并且控制总线上的信号完整性得到改善。

公开(公告)号：US20070015409A1

公开(公告)日：2007-01-18

申请号：US11440069

申请日：2006-05-25

Applicant: Nicolas Imbert ,  Charles Chuc

Inventor： Nicolas Imbert ,  Charles Chuc

IPC: H01R13/648

CPC classification number: H05K7/1459 ,  H01R12/52 ,  H01R31/005 ,  H05K1/0289 ,  H05K1/14 ,  H05K1/148 ,  H05K7/1441 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09972

Abstract: A device (20) for interconnecting electrical bundles, includes a plurality of pluggable connection and cross-connect cards (34 to 38) for the electrical bundles. The device further includes a “main” printed circuit (28, 28b) fitted with connectors or slots (29 to 33) designed and arranged to receive the pluggable cards, the printed circuit having a plurality of parallel tracks (46), each enabling two tracks (61 to 63, 68) or tracks starters (70 to 72) provided respectively on two distinct pluggable cards plugged in the connectors of the main printed circuit to be put to the same potential, each of the parallel tracks (46) being in contact with a respective pin (50, 150) of a plurality of connectors of the main printed circuit.

Abstract translation: 用于互连电束的装置（20）包括用于电束的多个可插拔连接和交叉连接卡（34至38）。 该装置还包括装配有设计和布置成接收可插拔卡的连接器或槽（29至33）的“主”印刷电路（28,28b），印刷电路具有多个平行轨道（46），每个启用 两个轨道（61至63,68）或轨道起动器（70至72）分别设置在插入主印刷电路的连接器中以插入相同电位的两个不同的可插拔卡上，每个平行轨道（46）为 与主印刷电路的多个连接器的相应销（50,150）接触。

公开(公告)号：US20060290440A1

公开(公告)日：2006-12-28

申请号：US11165982

申请日：2005-06-24

Applicant: John Benham ,  John Critchlow

Inventor： John Benham ,  John Critchlow

IPC: H01P5/04

CPC classification number: H01P5/02 ,  G01R31/2818 ,  G01R31/2822 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/09254

Abstract: According to some embodiments, a signal line associated with a printed circuit board is provided. In addition, a conductive trace is electrically connected to a portion of the signal line. At least a portion of the conductive trace may be offset from the signal line, and a dielectric layer may be provided between the signal line and the conductive trace to enhance electromagnetic coupling between them. As a result a hybrid resistance and electromagnetic coupling probe may be provided.

Abstract translation: 根据一些实施例，提供了与印刷电路板相关联的信号线。 此外，导电迹线电连接到信号线的一部分。 导电迹线的至少一部分可能偏离信号线，并且可以在信号线和导电迹线之间提供电介质层以增强它们之间的电磁耦合。 结果，可以提供混合电阻和电磁耦合探针。

公开(公告)号：US07142742B2

公开(公告)日：2006-11-28

申请号：US10710617

申请日：2004-07-25

Applicant: Jen-Yu Hsu ,  Chia-Yuan Pang ,  Song-Feng Tsai ,  Yao-Chou Tsai

Inventor： Jen-Yu Hsu ,  Chia-Yuan Pang ,  Song-Feng Tsai ,  Yao-Chou Tsai

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/42 ,  G11B7/00

CPC classification number: H05K1/148 ,  H05K3/361 ,  H05K2201/09254

Abstract: A method for arranging conducting lines of a flexible cable in an optical disk drive first confirms the pins having similar functions of all chips on a main board and a sub-board, and uses only one conducting line of the flexible cable to connect these pins. Therefore, the number of the conducting lines of the flexible cable can be reduced.

Abstract translation: 首先在光盘驱动器中布置柔性电缆的导线的方法，确认了在主板和子板上所有芯片具有相似功能的引脚，并且仅使用柔性电缆的一根导线来连接这些引脚。 因此，可以减少柔性电缆的导线数量。

公开(公告)号：US07013452B2

公开(公告)日：2006-03-14

申请号：US10395956

申请日：2003-03-24

Applicant: Torben Baras ,  Alan Michael Lyons ,  Carsten Metz

Inventor： Torben Baras ,  Alan Michael Lyons ,  Carsten Metz

IPC: G06F17/50

CPC classification number: H05K1/0248 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/09627 ,  H05K2201/0979

Abstract: An apparatus is disclosed that substantially reduces or eliminates the resonance that occurs in vias that connect the layers of a printed circuit board by electrically coupling a first transmission line in a circuit board to a second transmission line in a circuit board by two electrical paths having substantially the same electrical length. The two electrical paths are created by connecting the first transmission line to a first via which is in turn connected to a second via having a second transmission line with a plurality of connecting electrical paths between the two vias. In one illustrative embodiment, electrical traces are used to connect the top of the first via to the top of the second via and the bottom of the first via to the bottom of the second via.

Abstract translation: 公开了一种装置，其基本上减少或消除了在通过将电路板中的第一传输线电连接到电路板中的第二传输线的通孔中连接印刷电路板的层的通孔中发生的谐振， 相同的电气长度。 通过将第一传输线连接到第一通孔而产生两个电路径，第一通孔又连接到第二通孔，第二通孔具有在两个通孔之间具有多个连接电路径的第二传输线。 在一个说明性实施例中，电迹线用于将第一通孔的顶部连接到第二通孔的顶部和第一通孔的底部到第二通孔的底部。

公开(公告)号：US20050230845A1

公开(公告)日：2005-10-20

申请号：US11154829

申请日：2005-06-17

Applicant: Kohji Shinomiya

Inventor： Kohji Shinomiya

IPC: H05K1/18 ,  H01L23/50 ,  H01L25/04 ,  H01L25/18 ,  H05K1/02 ,  H01L23/48

CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: A portable telephone including an integrated circuit chip module with a first integrated circuit chip including a first power source pad for a first power voltage and an adjacent second power source pad for a second power voltage, the first power voltage being higher than the second power voltage, a second integrated circuit chip including a third power source pad for the first power voltage and an adjacent fourth power source pad for the second power voltage, and a wiring board including a first power source wire electrically connected to the first power source pad, a second power source wire electrically connected to the second power source pad, a third power source wire electrically connected to the third power source pad, and a fourth power source wire electrically connected to the fourth power source pad. Distance between the first and second power source wires is shorter than distance between the first or second power source wires and the third or fourth power source wires, and distance between the third and fourth power source wires is shorter than distance between the first or second power source wires and the third or fourth power source wires.

Abstract translation: 一种便携式电话，包括具有第一集成电路芯片的集成电路芯片模块，所述第一集成电路芯片包括用于第一电源电压的第一电源焊盘和用于第二电源电压的相邻的第二电源焊盘，所述第一电源电压高于所述第二电源电压 第二集成电路芯片，包括用于第一电源电压的第三电源焊盘和用于第二电源电压的相邻的第四电源焊盘;以及布线板，包括电连接到第一电源焊盘的第一电源线， 电连接到第二电源焊盘的第二电源线，与第三电源焊盘电连接的第三电源线，以及电连接到第四电源焊盘的第四电源线。 第一和第二电源线之间的距离短于第一或第二电源线与第三或第四电源线之间的距离，并且第三和第四电源线之间的距离短于第一或第二电源线之间的距离 源极线和第三或第四电源线。