公开(公告)号：US20150181706A1

公开(公告)日：2015-06-25

申请号：US14643230

申请日：2015-03-10

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer BONIFIELD ,  Byron WILLIAMS ,  Shrinivasan JAGANATHAN ,  David LARKIN ,  Dhaval Atul SARAIYA

IPC: H05K1/03 ,  H05K1/16 ,  H05K1/11 ,  H05K1/09

CPC classification number: H01L23/5223 ,  H01L23/49811 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/538 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14335 ,  H05K1/0256 ,  H05K1/0257 ,  H05K1/0262 ,  H05K1/0306 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/112 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0088 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0746 ,  H05K2201/09409 ,  H05K2201/0949 ,  H05K2201/09672 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

公开(公告)号：US20150173184A1

公开(公告)日：2015-06-18

申请号：US14628455

申请日：2015-02-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru KATO ,  Jun SASAKI ,  Satoshi ISHINO

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/03

CPC classification number: H05K1/0281 ,  H05K1/024 ,  H05K1/028 ,  H05K1/0298 ,  H05K1/032 ,  H05K1/09 ,  H05K2201/0141 ,  H05K2201/057 ,  H05K2201/0715 ,  H05K2201/09018 ,  H05K2201/09409

Abstract: A multilayer substrate that retains a curved state without causing fluctuations in electrical characteristics includes a main body including a plurality of insulating sheets to be stacked and made of a flexible material. A signal wire extends in the main body. A ground conductor is provided at a positive-direction side in a z-axis direction relative to the signal wire in the main body, and overlaps the signal line in a plan view seen from the z-axis direction. A ground conductor is provided on a negative-direction side in the z-axis direction relative to the signal wire in the main body, and overlaps the signal line in a plan view seen from the z-axis direction. The state in which the main body is curved so that the signal wire defines an arc is retained by plastic deformation of the ground conductors.

Abstract translation: 保持弯曲状态而不引起电特性波动的多层基板包括：主体，其包括要堆叠并由柔性材料制成的多个绝缘片。 信号线在主体中延伸。 接地导体相对于主体中的信号线在z轴方向的正方向侧设置，并且在从z轴方向看的俯视图中与信号线重叠。 接地导体相对于主体中的信号线在z轴方向的负方向侧设置，并且在从z轴方向观察的俯视图中与信号线重叠。 主体弯曲的状态使得信号线定义为电弧，由接地导体的塑性变形保持。

公开(公告)号：US09006584B2

公开(公告)日：2015-04-14

申请号：US13960406

申请日：2013-08-06

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Byron Williams ,  Shrinivasan Jaganathan ,  David Larkin ,  Dhaval Atul Saraiya

IPC: H05K1/16 ,  H05K1/03 ,  H05K1/09 ,  H05K3/00

CPC classification number: H01L23/5223 ,  H01L23/49811 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/538 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14335 ,  H05K1/0256 ,  H05K1/0257 ,  H05K1/0262 ,  H05K1/0306 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/112 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0088 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0746 ,  H05K2201/09409 ,  H05K2201/0949 ,  H05K2201/09672 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract translation: 电子隔离装置形成在单片基板上并且包括多个被动隔离部件。 隔离元件形成三个金属层。 通过无机PMD层将第一金属层与整体式衬底分离。 第二金属层与第一金属层分开一层二氧化硅。 第三金属层与第二金属层相隔至少20微米的聚酰亚胺或PBO。 隔离组件包括用于连接到其他设备的第三金属层上的焊盘。 在第三金属层上形成介电层，露出粘合垫。 隔离器件不含晶体管。

公开(公告)号：US08994176B2

公开(公告)日：2015-03-31

申请号：US13713034

申请日：2012-12-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Chiang Wu ,  Hsien-Wei Chen ,  Yu-Feng Chen ,  Chun-Hung Lin ,  Ming-Kai Liu ,  Chun-Lin Lu

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K1/0284 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/181 ,  H05K3/40 ,  H05K2201/09409 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

Abstract translation: 公开了用于包装模具中使用的用于插座的插入件的方法和装置。 插入件可以包括衬底上方的金属层。 可以在金属层的金属层的每个角落周围形成多个堤坝。 可以在插入器基板的两侧上形成大坝。 大坝围绕可能位于连接器如焊球的区域以连接到其他包装。 坝上可能形成非导电坝。 可以在金属层上方连接到连接器的封装下方形成底部填充物，并且包含在由角落处的堤坝包围的区域内，使得连接器被底部填充物良好地保护。 这样的堤坝也可以进一步形成在印刷电路板上。

公开(公告)号：US20150041190A1

公开(公告)日：2015-02-12

申请号：US13960406

申请日：2013-08-06

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer BONIFIELD ,  Byron WILLIAMS ,  Shrinivasan JAGANATHAN ,  David LARKIN ,  Dhaval Atul SARAIYA

IPC: H05K1/03 ,  H05K1/16 ,  H05K3/00 ,  H05K1/09

CPC classification number: H01L23/5223 ,  H01L23/49811 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/538 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14335 ,  H05K1/0256 ,  H05K1/0257 ,  H05K1/0262 ,  H05K1/0306 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/112 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0088 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0746 ,  H05K2201/09409 ,  H05K2201/0949 ,  H05K2201/09672 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract translation: 电子隔离装置形成在单片基板上并且包括多个被动隔离部件。 隔离元件形成三个金属层。 通过无机PMD层将第一金属层与整体式衬底分离。 第二金属层与第一金属层分开一层二氧化硅。 第三金属层与第二金属层相隔至少20微米的聚酰亚胺或PBO。 隔离组件包括用于连接到其他设备的第三金属层上的焊盘。 在第三金属层上形成介电层，露出粘合垫。 隔离器件不含晶体管。

公开(公告)号：US08952408B2

公开(公告)日：2015-02-10

申请号：US13710648

申请日：2012-12-11

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Tatsuaki Denda ,  Kazutaka Kobayashi

IPC: H01L33/00 ,  H01L33/60 ,  H05K1/02 ,  H01L21/50 ,  H05K1/11

CPC classification number: H01L33/60 ,  H01L21/50 ,  H01L2224/16245 ,  H01L2924/181 ,  H05K1/0203 ,  H05K1/0265 ,  H05K1/0274 ,  H05K1/111 ,  H05K2201/09409 ,  H05K2201/098 ,  H05K2201/099 ,  H05K2201/10106 ,  H05K2201/2054 ,  H01L2924/00012

Abstract: A light-emitting element mounting package includes a light-emitting element mounting portion that includes a plurality of wiring portions arranged interposing a predetermined gap between the wiring portions facing each other, and an insulating layer on which the light-emitting element mounting portion is mounted, wherein an upper surface of the light-emitting element mounting portion is exposed on the insulating layer, wherein cutout portions are formed on lower sides of side edges of the wiring portions and contact the insulating layer.

Abstract translation: 发光元件安装封装包括发光元件安装部分，该发光元件安装部分包括布置在彼此面对的布线部之间的预定间隙的多个布线部分和安装有发光元件安装部分的绝缘层 其中，所述发光元件安装部的上表面露出在所述绝缘层上，在所述布线部的侧缘的下侧形成有切口部，并与所述绝缘层接触。

公开(公告)号：US20150011832A1

公开(公告)日：2015-01-08

申请号：US13933145

申请日：2013-07-02

Applicant: GYRUS ACMI, INC. (d.b.a. Olympus Surgical Technologies America)

Inventor： Shai Finkman ,  Adi Navve

IPC: H01R12/71 ,  H01L27/146 ,  A61B1/00 ,  H01L23/00

CPC classification number: H01R12/712 ,  A61B1/00124 ,  A61B1/00131 ,  A61B1/051 ,  H01L24/81 ,  H01L27/1469 ,  H01R12/718 ,  H04N2005/2255 ,  H05K1/117 ,  H05K3/368 ,  H05K2201/094 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10151 ,  H05K2203/041 ,  H05K2203/049

Abstract: A connector for connection to terminals of an integrated circuit. The connector consists of a dielectric substrate having a first side and a second side. The connector has wire bond terminals which are attached to the first side of the substrate and configured to receive wire bonds connected to a first set of the terminals of the integrated circuit. The connector also has solder bump terminals, attached to the second side of the substrate so as to be insulated from the wire bond terminals, the solder bump terminals being configured to be coupled via solder balls with a second set of the terminals of the integrated circuit.

Abstract translation: 用于连接到集成电路的端子的连接器。 连接器由具有第一侧和第二侧的电介质基底构成。 连接器具有连接到基板的第一侧并且被配置为接收连接到集成电路的第一组端子的引线键合的引线接合端子。 连接器还具有焊料凸块端子，附接到基板的第二面以与引线接合端子绝缘，焊料凸块端子被配置为通过焊球与集成电路的第二组端子耦合 。

公开(公告)号：US20140235106A1

公开(公告)日：2014-08-21

申请号：US14222446

申请日：2014-03-21

Applicant: Spansion LLC

Inventor： Che Seong LEE ,  Kaseasan EDUMBAN

IPC: H01R13/04

CPC classification number: H01R13/04 ,  G01R31/2818 ,  H05K1/0268 ,  H05K1/117 ,  H05K2201/09409 ,  H05K2201/10325

Abstract: An electronic structure (for example a reliability board or a cycling control module) has a body including a body portion insertable into a connector. A plurality of contact structures are provided on a side of the body portion, each contact structure comprising a first contact and a second contact spaced from the first contact, with the first and second contacts of each contact structure being aligned in the direction of insertion of the body portion into the connector. A corresponding second plurality of contact structures is provided on a side of the body portion opposite the first—mentioned side. These contacts connect with respective corresponding contacts of the connector.

Abstract translation: 电子结构（例如可靠性板或循环控制模块）具有主体，该主体包括可插入到连接器中的主体部分。 多个接触结构设置在主体部分的一侧上，每个接触结构包括第一触点和与第一触点间隔开的第二触点，每个触头结构的第一和第二触点沿插入方向对准 主体部分插入连接器。 相应的第二多个接触结构设置在与第一侧相对的主体部分的一侧上。 这些触点与连接器的相应的相应的触点相连。

公开(公告)号：US20140167263A1

公开(公告)日：2014-06-19

申请号：US13713034

申请日：2012-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kai-Chiang Wu ,  Hsien-Wei Chen ,  Yu-Feng Chen ,  Chun-Hung Lin ,  Ming-Kai Liu ,  Chun-Lin Lu

IPC: H01L23/00 ,  H01L21/50

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K1/0284 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/181 ,  H05K3/40 ,  H05K2201/09409 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

Abstract translation: 公开了用于包装模具中使用的用于插座的插入件的方法和装置。 插入件可以包括衬底上方的金属层。 可以在金属层的金属层的每个角落周围形成多个堤坝。 可以在插入器基板的两侧上形成大坝。 大坝围绕可能位于连接器如焊球的区域以连接到其他包装。 坝上可能形成非导电坝。 可以在金属层上方连接到连接器的封装下方形成底部填充物，并且包含在由角落处的堤坝包围的区域内，使得连接器被底部填充物良好地保护。 这样的堤坝也可以进一步形成在印刷电路板上。

公开(公告)号：US08624273B2

公开(公告)日：2014-01-07

申请号：US13118575

申请日：2011-05-31

Applicant: Tzu-Hao Chao

Inventor： Tzu-Hao Chao

IPC: H01L29/205

CPC classification number: H05K1/181 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09254 ,  H05K2201/09409 ,  H05K2201/10106 ,  Y02P70/611 ,  H01L2924/00

Abstract: A multi-chip package comprises a plurality of chip pads and a plurality of LED chips. The chip pads are arranged in an M×N array, M and N each a positive integer greater than 1. A peripheral area of each chip pad comprises a respective first bonding pad, a respective second bonding pad, and a respective third bonding pad arranged in sequence in a clockwise direction. A first orientation of the respective first to third bonding pads in a first row of the N rows differs from a second orientation of the respective first to third bonding pads in a second row of the N rows by 90 degrees. Each of the LED chips is disposed on a respective one of the chip pads and electrically connected to two of the respective first to third bonding pads on a same side of the respective LED chip.

Abstract translation: 多芯片封装包括多个芯片焊盘和多个LED芯片。 芯片焊盘布置成M×N阵列，M和N各自为大于1的正整数。每个芯片焊盘的外围区域包括相应的第一焊盘，相应的第二焊盘和相应的第三焊盘， 顺时针方向。 N行的第一行中的相应的第一至第三接合焊盘的第一取向与N行的第二行中的相应的第一至第三接合焊盘的第二取向不同，90度。 每个LED芯片设置在相应的一个芯片焊盘上，并且在相应的LED芯片的同一侧上电连接到相应的第一至第三焊盘中的两个。