公开(公告)号：US06815313B2

公开(公告)日：2004-11-09

申请号：US10033397

申请日：2001-12-27

Applicant: Hiromi Yatsuda

Inventor： Hiromi Yatsuda

IPC: H01L21301

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L24/97 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/10666 ,  H05K2203/1147 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: A first substrate has a plurality of bumps and a second substrate has a plurality of openings at positions in registration with the plurality of bumps when the first and second substrates are placed one on top of the other in a confronting manner. The first and second substrates are put together by fusing a sealing wall formed on the second substrate, to hermetically seal an electronic device lying on the first substrate therein. Gas that may be generated upon fusing of the sealing wall can be effectively removed through the openings in the second substrate.

Abstract translation: 第一基板具有多个凸块，并且当第一和第二基板以相对的方式一个放置在另一个基板上时，第二基板在与多个凸块对准的位置处具有多个开口。 通过将形成在第二基板上的密封壁融合，将第一和第二基板放置在一起，将位于其上的第一基板上的电子设备密封。 可以通过第二基板中的开口有效地去除在密封壁融合时产生的气体。

公开(公告)号：US06802120B2

公开(公告)日：2004-10-12

申请号：US10191986

申请日：2002-07-10

Applicant: Toshiki Uehara

Inventor： Toshiki Uehara

IPC: H05K310

CPC classification number: H05K1/112 ,  H05K1/18 ,  H05K3/4069 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/035 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10189 ,  H05K2201/1059 ,  H05K2203/1572 ,  Y10S29/016 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of manufacturing a printed wiring board, enabling insertion components to be mounted on both sides thereof, including: a) providing first and second copper-clad laminates, including plated through-holes thereon; b) hot-pressing the laminates with each other and a first prepreg bonding sheet therebetween, so that the through-holes are closed by the prepreg to form non-through holes; c) laminating a second prepreg on each of the surfaces of the composite laminate; d) covering the opening of respective non-through holes with a heat resistant resin film; e) laminating one-side copper-clad laminate on each of the surfaces of the product of (d), with the copper side out, followed by hot-pressing; f) etching the copper sides to form outer layer circuit patterns; g) removing the base material layers covering the openings of the non-through holes; and h) removing the heat resistant resin films of the openings of the non-through holes.

Abstract translation: 一种制造印刷电路板的方法，其能够在两侧安装插入部件，包括：a）提供第一和第二铜包覆层压板，其上包括镀覆的通孔; b）将层叠体彼此热压，并在其间进行第一预浸料接合片，使得通孔被预浸料坯封闭以形成非通孔; c）在复合层压板的每个表面上层压第二预浸料; d）用耐热树脂膜覆盖各个非通孔的开口; e）在（d）的产品的每个表面上层叠一面覆铜层压板，将铜侧排出，然后热压; f）蚀刻铜边以形成外层电路图案; g）去除覆盖非通孔的开口的基材层; 以及h）去除非通孔的开口的耐热树脂膜。

公开(公告)号：US20040129453A1

公开(公告)日：2004-07-08

申请号：US10337949

申请日：2003-01-07

Inventor： David W. Boggs ,  Daryl Sato ,  John Dungan

IPC: H05K001/11 ,  H01R012/04

CPC classification number: H05K1/112 ,  H05K3/4076 ,  H05K3/421 ,  H05K2201/09245 ,  H05K2201/09472 ,  H05K2201/09509

Abstract: Embodiments of substrate in accordance with the present invention provide interconnect cavities for direct interconnection between SMT components and internal conductive inner layers, as well as surface outer layers. Interconnect cavities eliminate the need for through hole vias and require less substrate surface area and internal volume. Each interconnect cavity comprises a cavity extending from the substrate surface to an adjacent internal conductive inner layer directly beneath the cavity. The cavity extends through a conductive outer layer on the substrate surface. The cavity has a conductive liner interconnected with the outer layer and the inner layer forming a cup-shaped conductive depression interconnecting the outer layer with the inner layer.

Abstract translation: 根据本发明的衬底的实施例提供用于SMT部件和内部导电内层之间以及表面外层的直接互连的互连腔。 互连腔消除了对通孔的需要，并且需要较少的衬底表面积和内部体积。 每个互连腔包括从衬底表面延伸到空腔正下方的相邻内部导电内层的空腔。 空腔延伸穿过衬底表面上的导电外层。 空腔具有与外层互连的导电衬垫，内层形成将外层与内层互连的杯形导电凹部。

公开(公告)号：US06759739B2

公开(公告)日：2004-07-06

申请号：US10281163

申请日：2002-10-28

Applicant: Jyunichi Nakamura ,  Tadashi Kodaira ,  Shunichiro Matsumoto ,  Hironari Aratani ,  Takanori Tabuchi ,  Takeshi Chino

Inventor： Jyunichi Nakamura ,  Tadashi Kodaira ,  Shunichiro Matsumoto ,  Hironari Aratani ,  Takanori Tabuchi ,  Takeshi Chino

IPC: H01L2312

CPC classification number: H05K3/0061 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/205 ,  H05K3/3457 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/0969 ,  H05K2201/2009 ,  H05K2203/1536

Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.

Abstract translation: 一种用于半导体器件的多层衬底，其具有由多组导体层和绝缘层形成的多层衬底本体，并且具有用于安装半导体元件的面和用于外部连接端子的另一面，用于安装的面 半导体器件设置有衬底，衬底通过该焊盘连接到要安装在其上的半导体元件，并且用于外部连接端子的面设置有衬底，衬底通过该衬垫连接到外部电路，其中加强板是 分别连接到用于在其上安装半导体元件的面和多层基板主体的外部连接端子的表面。

公开(公告)号：US20040087077A1

公开(公告)日：2004-05-06

申请号：US10693380

申请日：2003-10-24

Inventor： Warren M. Farnworth ,  Alan G. Wood

IPC: H01L021/8238

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81224 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H05K2201/09472 ,  H05K2201/10977 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655

Abstract: A semiconductor component includes a substrate, bonding pads on the substrate, and external contacts bonded to the bonding pads. Exemplary external contacts include solder balls, solder bumps, solder columns, TAB bumps and stud bumps. Preferably the external contacts are arranged in a dense array, such as a ball grid array (BGA), or fine ball grid array (FBGA). The component also includes a polymer support member configured to strengthen the external contacts, absorb forces applied to the external contacts, and prevent separation of the external contacts from the bonding pads. In a first embodiment, the polymer support member comprises a cured polymer layer on the substrate, which encompasses the base portions of the external contacts. In a second embodiment, the polymer support member comprises support rings which encompass the base portions of the external contacts. In either embodiment the polymer support member transfers forces applied to the external contacts away from the interface with the bonding pads, and into the center of the contacts.

Abstract translation: 半导体部件包括基板，基板上的接合焊盘和接合到接合焊盘的外部触头。 示例性外部触点包括焊球，焊料凸块，焊料柱，TAB凸块和凸块凸块。 优选地，外部接触件以密集阵列布置，例如球栅阵列（BGA）或细球栅阵列（FBGA）。 该部件还包括聚合物支撑构件，其构造成加强外部触点，吸收施加到外部触点的力，并防止外部触头与接合焊盘分离。 在第一实施例中，聚合物支撑构件包括在基底上的固化的聚合物层，其包围外部触点的基部。 在第二实施例中，聚合物支撑构件包括包围外部触点的基部的支撑环。 在任一实施例中，聚合物支撑构件传递施加到外部触头的力，远离与接合焊盘的界面，并且进入触点的中心。

公开(公告)号：US20040051171A1

公开(公告)日：2004-03-18

申请号：US10649005

申请日：2003-08-26

Inventor： Kee Yean Ng ,  Gurbir Singh

IPC: H01L023/48

CPC classification number: H01L33/486 ,  H01C1/14 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49805 ,  H01L24/48 ,  H01L24/73 ,  H01L33/62 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/12041 ,  H01L2924/181 ,  H05K3/3442 ,  H05K2201/09154 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/10106 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A surface mountable electronic device includes a body with a first surface for mounting the device. The first surface has recessed portions therein. Electrical contacts are provided in the first surface. The electrical contacts include first portions that form at least a portion of at least one inner surface of said recessed portions.

Abstract translation: 可表面安装的电子设备包括具有用于安装设备的第一表面的主体。 第一表面在其中具有凹部。 电触头设置在第一表面。 电触点包括形成所述凹部的至少一个内表面的至少一部分的第一部分。

公开(公告)号：US20040012930A1

公开(公告)日：2004-01-22

申请号：US10621194

申请日：2003-07-15

Inventor： Ford B. Grigg

IPC: H05K013/00 ,  H05K001/14 ,  H05K003/34

CPC classification number: H05K3/3436 ,  H01L2224/4824 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H05K3/3452 ,  H05K3/3478 ,  H05K3/3489 ,  H05K2201/09472 ,  H05K2201/0989 ,  H05K2201/10977 ,  H05K2203/0195 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/0537 ,  H05K2203/058 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49169 ,  Y10T29/49171

Abstract: Packaged microelectronic devices, methods of manufacturing packaged microelectronic devices, and method of mounting packaged microelectronic devices to printed circuit boards. One embodiment can include a die, an interposer substrate, a solder-ball, and a dielectric compound. The die can have an integrated circuit and at least one bond-pad coupled to the integrated circuit. The interposer substrate is coupled to the die and can have at least one ball-pad electrically coupled to the bond-pad on the die. The interposer substrate can also have a trace line adjacent to the ball-pad, and a solder-mask having an opening over the ball-pad. The solder-ball can contact the ball-pad in the opening. The dielectric compound can insulate the ball-pad and the solder-ball from an exposed portion of the adjacent trace line in the opening.

Abstract translation: 封装的微电子器件，制造封装的微电子器件的方法以及将封装的微电子器件安装到印刷电路板的方法。 一个实施例可以包括管芯，插入器衬底，焊球和电介质化合物。 芯片可以具有集成电路和耦合到集成电路的至少一个接合焊盘。 插入器基板耦合到管芯并且可以具有至少一个电焊接到管芯上的焊盘的球焊盘。 插入器基板还可以具有与球垫相邻的迹线，以及在球垫上具有开口的焊接掩模。 焊球可以接触开口中的球垫。 电介质化合物可以使球垫和焊球与开口中的相邻轨迹线的暴露部分绝缘。

公开(公告)号：US20040004285A1

公开(公告)日：2004-01-08

申请号：US10606717

申请日：2003-06-26

Inventor： Johnny Cheng ,  Joyce Hsu

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L21/486 ,  H01L23/49816 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/3457 ,  H05K3/423 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2203/041 ,  H05K2203/0733 ,  H01L2924/00014

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the viva is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract translation: 通常，球栅或芯片级封装上的半导体芯片和外部焊球接触之间的主电连接是通过延伸穿过电介质衬底的通孔。 通孔直径和深度之间的纵横比对于在印刷电路板组装过程中可靠且高产量的焊球附着至关重要。 BGA焊球接触的良好的球粘附性和可靠性通过在每个通孔中部分镀覆可固化的可焊接导体芯来控制衬底通孔的纵横比来实现。 公开了一种改进的通孔结构，其中减少了血液的深度，而没有替代方法的负面影响，例如较薄的底物或更宽的通孔。

公开(公告)号：US06642625B2

公开(公告)日：2003-11-04

申请号：US10299131

申请日：2002-11-19

Applicant: Thomas H. Dozier, II ,  Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu ,  David V. Pederson ,  Michael A. Stadt

Inventor： Thomas H. Dozier, II ,  Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu ,  David V. Pederson ,  Michael A. Stadt

IPC: H01L2304

CPC classification number: G01R1/0408 ,  B23K3/087 ,  G01R1/0416 ,  G01R1/0466 ,  G01R31/2886 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/5385 ,  H01L24/72 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/73251 ,  H01L2224/8114 ,  H01L2224/81901 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/119 ,  H05K3/308 ,  H05K3/325 ,  H05K2201/0311 ,  H05K2201/09472 ,  H05K2201/09827 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/4914 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49208 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  H01L2924/00014 ,  H01L2224/72

Abstract: Temporary connections to spring contact elements extending from an electronic component such as a semiconductor device are made by urging the electronic component, consequently the ends of the spring contact elements, vertically against terminals of an interconnection substrate, or by horizontally urging terminals of an interconnection substrate against end portions of the spring contact elements. A variety of terminal configurations are disclosed.

Abstract translation: 从诸如半导体器件的电子部件延伸的弹簧接触元件的临时连接是通过推动电子部件，因此弹簧接触元件的端部垂直地抵靠互连基板的端子，或者通过水平推动互连基板的端子 抵抗弹簧接触元件的端部。 公开了各种终端配置。

公开(公告)号：US06628128B1

公开(公告)日：2003-09-30

申请号：US09651860

申请日：2000-08-30

Applicant: Warren M. Farnworth ,  Derek J. Gochnour ,  David R. Hembree

Inventor： Warren M. Farnworth ,  Derek J. Gochnour ,  David R. Hembree

IPC: G01R3102

CPC classification number: H05K1/112 ,  G01R1/0483 ,  H05K3/325 ,  H05K2201/09472 ,  H05K2201/09827 ,  H05K2201/10734

Abstract: A BGA test socket for use in standard testing and burn-in testing of BGA dies and method for testing such dies is disclosed wherein a die contact insert made of silicon or ceramic using standard IC fabrication technology is used. Through using such an insert, even small scale (pitch) BGA dies can be reliably tested including chip scale packaged (“CSP”) BGA dies. Furthermore, using such an insert allows a conventional socket to be adapted for use with a wide variety of both BGA dies and other varieties. A method for using the device is disclosed which overcomes current static electricity problems experienced in testing CSP BGA dies through closing the test socket before removing the die deposit probe.