公开(公告)号：US20170077023A1

公开(公告)日：2017-03-16

申请号：US15364143

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

Abstract translation: 半导体衬底包括：1）具有第一表面和与第一表面相对的第二表面的第一电介质结构; 2）具有与第三表面相对的第三表面和第四表面的第二介电结构，其中第四表面面向第一表面，第二介电结构限定从第三表面延伸到第四表面的通孔，其中腔是 由通孔和第一电介质结构限定; 3）设置在第一介电结构的第一表面上的第一图案化导电层; 以及4）第二图案化导电层，设置在所述第一介电结构的第二表面上并且包括至少一个导电迹线。 第一介电结构限定至少一个开口以暴露第二图案化导电层的一部分。

公开(公告)号：US20170062100A1

公开(公告)日：2017-03-02

申请号：US14833191

申请日：2015-08-24

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Kuniaki YOSUI

IPC: H01B13/00 ,  H01B13/06

CPC classification number: H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/115 ,  H05K3/246 ,  H05K3/363 ,  H05K3/4069 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/09181 ,  H05K2201/09527 ,  H05K2201/09572

Abstract: In a method for manufacturing a multilayer substrate, first, a via hole is formed in a first insulating layer and a second insulating layer and filled with conductive paste. Subsequently, the first insulating layer and the second insulating layer are stacked on each other. Next, the conductive paste is cured to form a via conductor while the first insulating layer and the second insulating layer are integrated through thermal pressing. Then, a penetrating hole that penetrates the via conductor in the laminating direction is formed.

Abstract translation: 在多层基板的制造方法中，首先，在第一绝缘层和第二绝缘层中形成通孔，并填充导电性糊料。 随后，第一绝缘层和第二绝缘层彼此堆叠。 接下来，通过热压将第一绝缘层和第二绝缘层一体化，使导电膏固化，形成通路导体。 然后，形成在层叠方向上贯通通孔导体的贯通孔。

公开(公告)号：US09380707B2

公开(公告)日：2016-06-28

申请号：US14090076

申请日：2013-11-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi Shimizu ,  Akio Rokugawa ,  Toshinori Koyama ,  Wataru Kaneda

IPC: H05K3/02 ,  H01L23/48 ,  H05K3/00 ,  H05K3/20 ,  H01L23/498 ,  H01L21/48 ,  H05K3/46

CPC classification number: H05K3/007 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/12044 ,  H01L2924/15311 ,  H05K3/20 ,  H05K3/205 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/09527 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a wiring substrate includes: preparing a laminated plate of a metal layer and an insulating layer; adhering the laminated plate to a first support body facing the metal layer; and forming a first wiring layer with vias extending through the insulating layer and first pads exposed from a first surface of the insulating layer. The method also includes: separating a multilayer structure including the metal, insulating, and first wiring layer from the first support body; adhering the multilayer structure to a second support body facing the first wiring layer; removing the metal layer; forming a plurality of second wiring layers including second pads connected to the vias and exposed from a second surface of the insulating layer opposite the first surface; and separating the insulating, the first wiring, and the plurality of second wiring layers from the second support body, to obtain the wiring substrate.

Abstract translation: 制造布线基板的方法包括：制备金属层和绝缘层的层压板; 将所述层压板粘附到面对所述金属层的第一支撑体; 以及形成具有延伸穿过所述绝缘层的通孔的第一布线层和从所述绝缘层的第一表面暴露的第一焊盘。 该方法还包括：从第一支撑体分离包括金属，绝缘和第一布线层的多层结构; 将所述多层结构粘附到面对所述第一布线层的第二支撑体; 去除金属层; 形成多个第二布线层，所述第二布线层包括连接到所述通孔并从所述绝缘层的与所述第一表面相对的第二表面露出的第二焊盘; 并且从第二支撑体分离绝缘体，第一布线和多个第二布线层，以获得布线基板。

公开(公告)号：US09204541B2

公开(公告)日：2015-12-01

申请号：US13941066

申请日：2013-07-12

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Shunsuke Chisaka ,  Hiroshi Somada ,  Kosuke Nakano ,  Noboru Kato

IPC: H05K1/09 ,  H05K1/02 ,  H05K1/18 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/092 ,  H01L2224/16225 ,  H01L2924/1533 ,  H05K1/0271 ,  H05K1/115 ,  H05K1/185 ,  H05K3/0052 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0305 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2203/0554 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/49165

Abstract: The present invention provides a multilayer circuit board that includes a plurality of resin layers, conductive wiring layers, and via-hole conductors. Each of the resin layers includes a resin sheet containing a resin and a conductive wiring layer disposed on at least one surface of the resin sheet. The via-hole conductors contain an intermetallic compound having a melting point of 300° C. or more produced by a reaction between a first metal composed of Sn or an alloy containing 70% by weight or more Sn and a second metal composed of a Cu—Ni alloy or a Cu—Mn alloy. The second metal has a higher melting point than the first metal.

Abstract translation: 本发明提供一种多层电路板，其包括多个树脂层，导电布线层和通孔导体。 每个树脂层包括含有树脂的树脂片和布置在树脂片的至少一个表面上的导电布线层。 通孔导体含有由Sn组成的第一金属或含有70重量％以上的Sn的合金与由Cu组成的第二金属之间的反应产生的熔点为300℃以上的熔点的金属间化合物 -Ni合金或Cu-Mn合金。 第二金属具有比第一金属更高的熔点。

公开(公告)号：US20150137348A1

公开(公告)日：2015-05-21

申请号：US14606425

申请日：2015-01-27

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro KURITA ,  Masaya KAWANO ,  Koji SOEJIMA

IPC: H01L23/522

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract translation: 在传统的电子设备及其制造方法中，由于在焊球侧的互连层中使用的树脂受到限制，妨碍了电子设备的成本的降低。 电子设备包括互连层（第一互连层）和互连层（第二互连层）。 第二互连层形成在第一互连层的下表面上。 第二互连层的面积比第一互连层的面积大，并且从第一互连层延伸到外部。

公开(公告)号：US09012785B2

公开(公告)日：2015-04-21

申请号：US14047623

申请日：2013-10-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito Otsubo

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K1/028 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/09 ,  H05K2201/09527 ,  H05K2201/096 ,  Y10T29/49165 ,  Y10T428/1259 ,  Y10T428/24355 ,  Y10T428/31663

Abstract: A flexible multilayer substrate includes a multilayer body including a plurality of laminated resin layers. The multilayer body includes an innermost surface, which is a surface on an inner side when the substrate is bent, and an outermost surface, which is a surface on an outer side when the substrate is bent. Each of the plurality of resin layers includes a skin layer on one surface. Lamination of the multilayer body includes a skin layer joint plane at one location at a central portion in the thickness direction, and the skin layer and other surface come in contact with each other at another location along the central portion in the thickness direction. A skin layer joint plane is arranged on a side closer to the innermost surface than a central plane in the thickness direction of the multilayer body.

Abstract translation: 柔性多层基板包括具有多个层叠树脂层的多层体。 所述多层体包含最内表面，所述最内表面是当所述基材弯曲时在内侧的表面，以及最外表面，所述最外表面是当所述基材弯曲时在外侧的表面。 多个树脂层中的每一个在一个表面上包括表皮层。 多层体的层叠包括在厚度方向的中央部的一个位置处的表皮层接合面，并且表皮层和其他表面在厚度方向上沿着中心部分的另一位置彼此接触。 表皮层接合面布置在比多层体的厚度方向上的中心平面更靠近最内表面的一侧。

公开(公告)号：US20140346681A1

公开(公告)日：2014-11-27

申请号：US14455336

申请日：2014-08-08

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro KURITA ,  Masaya KAWANO ,  Koji SOEJIMA

IPC: H01L23/522

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

公开(公告)号：US20140150258A1

公开(公告)日：2014-06-05

申请号：US14090076

申请日：2013-11-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Akio ROKUGAWA ,  Toshinori KOYAMA ,  Wataru KANEDA

IPC: H05K3/46

CPC classification number: H05K3/007 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/12044 ,  H01L2924/15311 ,  H05K3/20 ,  H05K3/205 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/09527 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A wiring substrate includes a core portion and a wiring portion. The core portion includes a wiring layer and an organic resin core substrate. The wiring portion includes wiring layers and organic resin insulative layers. The wiring layer of the core portion is formed in a state in which the organic resin core substrate is supported by a support body. The wiring layers of the wiring portion are formed in a state in which the organic resin core substrate is adhered to a support body and the wiring layer of the core portion faces toward the support body.

Abstract translation: 布线基板包括芯部和布线部。 芯部包括布线层和有机树脂芯基板。 布线部分包括布线层和有机树脂绝缘层。 芯部的布线层形成为有机树脂芯基板由支撑体支撑的状态。 布线部分的布线层形成为有机树脂芯基板粘附到支撑体并且芯部的布线层朝向支撑体的状态。

公开(公告)号：US08604349B2

公开(公告)日：2013-12-10

申请号：US13453229

申请日：2012-04-23

Applicant: Norio Sakai

Inventor： Norio Sakai

IPC: H05K1/03 ,  H05K1/00 ,  H05K1/11

CPC classification number: H05K3/4617 ,  H05K1/186 ,  H05K3/4632 ,  H05K3/4691 ,  H05K2201/0129 ,  H05K2201/0191 ,  H05K2201/09527 ,  H05K2201/096 ,  Y10T156/10

Abstract: A multilayer substrate includes a plurality of stacked thermoplastic resin layers each including an in-plane conductive pattern provided on one principal surface thereof and an interlayer conductive portion arranged to penetrate through the thermoplastic resin layer in a thickness direction. The plurality of thermoplastic resin layers include a first thermoplastic resin layer and a second thermoplastic resin layer, a stacking direction of which is inverted with respect to a stacking direction of the first thermoplastic resin layer. The second thermoplastic resin layer is thicker than the first thermoplastic resin layer. One end in the thickness direction of the interlayer conductive portion provided in the second thermoplastic resin layer is connected with the interlayer conductive portion of the thermoplastic resin layer adjacent to the second thermoplastic resin layer in the thickness direction such that the in-plane conductive pattern is not interposed therebetween.

Abstract translation: 多层基板包括多个堆叠的热塑性树脂层，每个层叠的热塑性树脂层包括设置在其一个主表面上的面内导电图案和布置成在厚度方向上穿透热塑性树脂层的层间导电部分。 多个热塑性树脂层包括第一热塑性树脂层和第二热塑性树脂层，层叠方向相对于第一热塑性树脂层的层叠方向反转。 第二热塑性树脂层比第一热塑性树脂层厚。 设置在第二热塑性树脂层中的层间导电部分的厚度方向的一端与厚度方向上与第二热塑性树脂层相邻的热塑性树脂层的层间导电部分连接，使得面内导电图案为 不插入其间。

公开(公告)号：US20130299219A1

公开(公告)日：2013-11-14

申请号：US13941066

申请日：2013-07-12

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Shunsuke Chisaka ,  Hiroshi Somada ,  Kosuke Nakano ,  Noboru Kato

IPC: H05K1/09 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K1/092 ,  H01L2224/16225 ,  H01L2924/1533 ,  H05K1/0271 ,  H05K1/115 ,  H05K1/185 ,  H05K3/0052 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0305 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2203/0554 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/49165

Abstract: The present invention provides a multilayer circuit board that includes a plurality of resin layers, conductive wiring layers, and via-hole conductors. Each of the resin layers includes a resin sheet containing a resin and a conductive wiring layer disposed on at least one surface of the resin sheet. The via-hole conductors contain an intermetallic compound having a melting point of 300° C. or more produced by a reaction between a first metal composed of Sn or an alloy containing 70% by weight or more Sn and a second metal composed of a Cu—Ni alloy or a Cu—Mn alloy. The second metal has a higher melting point than the first metal.

Abstract translation: 本发明提供一种多层电路板，其包括多个树脂层，导电布线层和通孔导体。 每个树脂层包括含有树脂的树脂片和布置在树脂片的至少一个表面上的导电布线层。 通孔导体含有由Sn组成的第一金属或含有70重量％以上的Sn的合金与由Cu组成的第二金属之间的反应产生的熔点为300℃以上的熔点的金属间化合物 -Ni合金或Cu-Mn合金。 第二金属具有比第一金属更高的熔点。