公开(公告)号：US20170306481A1

公开(公告)日：2017-10-26

申请号：US15509662

申请日：2015-09-08

Applicant: JSR CORPORATION

Inventor： Hitoshi HAMAGUCHI ,  Kenrou TANAKA ,  Kenzou OOKITA ,  Keisuke KURIYAMA

IPC: C23C16/44 ,  H05K3/00 ,  G03F7/20 ,  G03F7/039 ,  C23C16/56 ,  C09D133/16 ,  C09D133/14 ,  C09D133/10 ,  C09D129/10 ,  H05K3/12 ,  B05D3/06

CPC classification number: C23C16/44 ,  B05D3/06 ,  B29C59/16 ,  C08F257/00 ,  C08F265/04 ,  C08F289/00 ,  C08J7/047 ,  C08J2355/02 ,  C08J2369/00 ,  C09D129/10 ,  C09D133/10 ,  C09D133/14 ,  C09D133/16 ,  C09D151/003 ,  C23C16/56 ,  G03F7/0046 ,  G03F7/039 ,  G03F7/0392 ,  G03F7/18 ,  G03F7/20 ,  G03F7/24 ,  H05K3/0023 ,  H05K3/12 ,  H05K2201/0166 ,  C08F216/1408

Abstract: The present invention relates to: a method of producing a structure having a recessed pattern; a resin composition; a method of forming an electroconductive film; an electronic circuit; and an electronic device. The method of producing a structure having a recessed pattern includes the following steps (i) and (ii), and the recessed pattern has a film thickness that is thinner by 5% to less than 90% with respect to that of a coating film obtained in the step (i): (i) the step of forming a coating film on a non-flat surface of a structure using a resin composition which includes an acid-dissociable group-containing polymer and an acid generator; and (ii) the step of forming a recess by subjecting a prescribed part of a portion of the coating film to irradiation with radiation.

公开(公告)号：US09666450B2

公开(公告)日：2017-05-30

申请号：US15099690

申请日：2016-04-15

Applicant: Tessera, Inc.

Inventor： Kazuo Sakuma ,  Philip Damberg ,  Belgacem Haba

IPC: H01L21/00 ,  H01L21/48 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H01L23/31 ,  H05K3/00 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L23/3142 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/01 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0284 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/002 ,  H05K2201/0166 ,  H01L2924/00

Abstract: An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.

公开(公告)号：US09318460B2

公开(公告)日：2016-04-19

申请号：US14513563

申请日：2014-10-14

Applicant: Tessera, Inc.

Inventor： Kazuo Sakuma ,  Philip Damberg ,  Belgacem Haba

IPC: H01L23/498 ,  H01L23/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09

CPC classification number: H01L21/4853 ,  H01L23/3142 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/01 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0284 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/002 ,  H05K2201/0166 ,  H01L2924/00

Abstract: An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.

Abstract translation: 互连衬底包括限定第一和第二横向方向的至少一个布线层的多个导电元件。 导电突起，用于粘合到基板外部的至少一个部件的导电触点，从导电元件延伸到至少一个布线层之上。 导电突起具有远离导电元件的端部和导电元件与端部之间的颈部。 端部具有在至少一个横向方向上从颈部部分向外延伸的下表面。 衬底还包括覆盖导电元件并且沿着颈部部分至少向下表面向上延伸的电介质层。 导电突起之间的电介质层的至少部分凹陷在下表面的高度之下。

公开(公告)号：US20160062242A1

公开(公告)日：2016-03-03

申请号：US14888244

申请日：2014-04-15

Applicant: JSR CORPORATION

Inventor： Hitoshi HAMAGUCHI ,  Kenrou TANAKA ,  Kenzou OOKITA ,  Keisuke KURIYAMA

IPC: G03F7/38 ,  H05K1/02 ,  G03F7/039 ,  H05K3/28 ,  G03F7/16 ,  G03F7/20

CPC classification number: G03F7/38 ,  G03F7/0046 ,  G03F7/039 ,  G03F7/0392 ,  G03F7/16 ,  G03F7/20 ,  G03F7/36 ,  H05K1/0296 ,  H05K3/107 ,  H05K3/1208 ,  H05K3/287 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/0166

Abstract: Provided is a method for manufacturing a substrate having a concave pattern to be used for forming a high-definition pattern while suppressing wet-spreading and bleeding of a film-forming ink, provided is a composition to be used for manufacturing the substrate, and provided are a method for forming a conductive film, an electronic circuit, and an electronic device.The method for manufacturing a substrate having a concave pattern includes: (i) a step of applying, on a substrate 1, a composition containing a polymer having an acid-dissociable group and an acid generator to form a coating film 2 and (ii) a step of irradiating a predetermined portion of the coating film 2 with radiation. The method for forming a conductive film includes applying a conductive film-forming ink on the concave pattern formed in the exposed portion of the coating film 2 and heating the ink to form a pattern 6. The electronic circuit and the electronic device are provided by using the method for forming a conductive film.

Abstract translation: 提供一种用于制造用于形成高清晰度图案的凹形图案的基板的方法，同时抑制成膜油墨的湿扩展和渗色，提供用于制造基板的组合物，并且提供 是形成导电膜，电子电路和电子器件的方法。 具有凹形图案的基板的制造方法包括：（i）在基板1上涂布含有具有酸解离基的聚合物和酸发生剂的组合物以形成涂膜2的步骤，（ii） 用辐射照射涂膜2的预定部分的步骤。 形成导电膜的方法包括在形成在涂膜2的暴露部分中的凹形图案上涂覆导电膜形成油墨并加热油墨以形成图案6.电子电路和电子设备通过使用 形成导电膜的方法。

公开(公告)号：US08866018B2

公开(公告)日：2014-10-21

申请号：US12352411

申请日：2009-01-12

Applicant: Pranabes K. Pramanik ,  Yuji Kageyama ,  Fujio Kuwako ,  Jin Hyun Hwang

Inventor： Pranabes K. Pramanik ,  Yuji Kageyama ,  Fujio Kuwako ,  Jin Hyun Hwang

IPC: H01B7/08 ,  H01G4/18 ,  H01G4/20 ,  H01G4/33 ,  H05K1/16

CPC classification number: H01G4/18 ,  H01G4/203 ,  H01G4/33 ,  H05K1/162 ,  H05K2201/0166 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09309 ,  Y10T156/10

Abstract: A thin laminate passive electrical device, such as, a capacitor, and a method of fabricating a thin laminate passive electrical device are provided. The passive electrical device includes two conductors, for example, copper foil conductors, separated by a dielectric having a first layer of a first material having a softening point temperature greater than a first temperature and a first layer of a second material having a softening point temperature less than the first temperature. The first temperature may be at least 150 degrees C. or higher. By providing a first layer having a higher softening point material, shorting across the conductors, that can be promoted by the fabrication process, is prevented. Methods of fabricating passive electrical devices are also disclosed.

Abstract translation: 提供了一种诸如电容器的薄层压无源电器件以及制造薄层压无源电器件的方法。 无源电器件包括两个导体，例如铜箔导体，由具有软化点温度大于第一温度的第一材料的第一层和第一材料的电介质隔开，第一层的第一材料具有软化点温度 小于第一温度。 第一温度可以为至少150摄氏度或更高。 通过提供具有较高软化点材料的第一层，可以防止通过制造工艺促进导体的短路。 还公开了制造无源电器件的方法。

公开(公告)号：US20140295148A1

公开(公告)日：2014-10-02

申请号：US14225094

申请日：2014-03-25

Applicant: Tamura Corporation

Inventor： Koji Maekawa ,  Naoya Kakiuchi ,  Yoshiki Takebayashi ,  Kazuhiro Horisawa

IPC: G03F7/038 ,  H05K1/03

CPC classification number: G03F7/038 ,  G03F7/031 ,  G03F7/032 ,  G03F7/0388 ,  H05K3/287 ,  H05K3/3452 ,  H05K2201/0166 ,  Y10T428/24802

Abstract: A photosensitive resin composition includes a carboxyl group-containing photosensitive resin, a photopolymerization initiator, a compound having an ethylenic unsaturated group, a non-reactive diluent, and an epoxy compound. The photopolymerization initiator includes an oxime ester compound and an aminocarbonyl compound having a tertiary amino group.

Abstract translation: 光敏树脂组合物包括含羧基的感光树脂，光聚合引发剂，具有烯属不饱和基团的化合物，非反应性稀释剂和环氧化合物。 光聚合引发剂包括肟酯化合物和具有叔氨基的氨基羰基化合物。

公开(公告)号：US20140147776A1

公开(公告)日：2014-05-29

申请号：US14127078

申请日：2012-06-15

Applicant: Nobuhito Ito ,  Masao Arima

Inventor： Nobuhito Ito ,  Masao Arima

IPC: G03F7/038

CPC classification number: G03F7/0384 ,  B32B27/38 ,  B32B27/42 ,  C08F287/00 ,  C08L61/14 ,  C08L63/10 ,  G03F7/038 ,  G03F7/0388 ,  H05K3/287 ,  H05K2201/0166

Abstract: Provided is an alkali-developable photocurable/thermosetting resin composition from which a cured coating film that has excellent thermal shock resistance and exhibits excellent PCT resistance, HAST resistance and electroless gold plating resistance, which are important as a solder resist for semiconductor packages, can be formed. The alkali-developable photocurable/thermosetting resin composition is characterized by comprising (A) a carboxyl group-containing photosensitive resin, (B) a photopolymerization initiator, (C) a block copolymer and (D) a thermosetting component.

Abstract translation: 本发明提供一种可显影的光固化/热固性树脂组合物，其作为半导体封装的阻焊剂是重要的，具有优异的耐热冲击性和优异的耐PCT耐性，耐HAST电阻和无电镀金电镀的固化涂膜可以是 形成。 碱显影性光固化/热固性树脂组合物的特征在于包含（A）含羧基的感光性树脂，（B）光聚合引发剂，（C）嵌段共聚物和（D）热固性组分。

公开(公告)号：US08308967B2

公开(公告)日：2012-11-13

申请号：US13006135

申请日：2011-01-13

Applicant: Katsuya Sakayori ,  Terutoshi Momose ,  Shigeki Kawano ,  Tomoko Togashi ,  Hiroko Amasaki ,  Nobuhiro Sakihama ,  Tsuyoshi Yamazaki ,  Michiaki Uchiyama ,  Hiroshi Yagi

Inventor： Katsuya Sakayori ,  Terutoshi Momose ,  Shigeki Kawano ,  Tomoko Togashi ,  Hiroko Amasaki ,  Nobuhiro Sakihama ,  Tsuyoshi Yamazaki ,  Michiaki Uchiyama ,  Hiroshi Yagi

IPC: C23F1/00 ,  H01B13/00

CPC classification number: H01L21/31138 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/32134 ,  H05K1/0346 ,  H05K1/056 ,  H05K3/002 ,  H05K3/064 ,  H05K2201/0154 ,  H05K2201/0166

Abstract: The present invention relates to an insulator as an insulating layer in a laminate which can inhibit dusting at the time of use, more particularly an electronic circuit component to which the insulator has been applied, particularly a wireless suspension. The insulator comprises a laminate of one or more insulation unit layers etchable by a wet process, the insulator having been subjected to plasma treatment after wet etching. The insulator exists mainly as an insulating layer in a laminate having a layer construction of first inorganic material layer-insulating layer-second inorganic material layer or a layer construction of inorganic material layer-insulating layer, and at least a part of the inorganic material layer has been removed to expose the insulating layer.

Abstract translation: 本发明涉及一种层叠体中的绝缘体，其可以在使用时抑制除尘，更具体地说，涉及绝缘体的电子电路部件，特别是无线悬架。 绝缘体包括可通过湿法蚀刻的一个或多个绝缘单元层的层压体，该绝缘体在湿蚀刻之后已进行等离子体处理。 绝缘体主要作为具有第一无机材料层 - 绝缘层 - 第二无机材料层的层结构或无机材料层 - 绝缘层的层结构的层叠体的绝缘体存在，并且至少一部分无机材料层 已经被去除以暴露绝缘层。

公开(公告)号：US08161638B2

公开(公告)日：2012-04-24

申请号：US12783806

申请日：2010-05-20

Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

IPC: H01K3/10

CPC classification number: H05K3/465 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/184 ,  H05K3/421 ,  H05K3/4661 ,  H05K2201/0166 ,  H05K2201/0195 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1056

Abstract: A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.

Abstract translation: 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。

公开(公告)号：US08141245B2

公开(公告)日：2012-03-27

申请号：US12344643

申请日：2008-12-29

Applicant: Kevin C. Olson ,  Alan E. Wang ,  Peter Elenius ,  Thomas W. Goodman

Inventor： Kevin C. Olson ,  Alan E. Wang ,  Peter Elenius ,  Thomas W. Goodman

IPC: H01K3/10

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T428/12361 ,  Y10T428/24322

Abstract: A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.

Abstract translation: 多层电路板的电路板或每个电路板包括涂覆有覆盖导电片的一个表面的绝缘顶层的导电片，覆盖导电片的另一表面的绝缘底层和覆盖 导电片的边缘。 绝缘中间层可以夹在多层电路板组件的一对相邻电路板之间。 无地通孔或通孔可以延伸通过一个或多个电路板，用于连接其相对表面上的电导体。