公开(公告)号：US20110005821A1

公开(公告)日：2011-01-13

申请号：US12922253

申请日：2009-03-25

Applicant: Tom Marttila

Inventor： Tom Marttila

IPC: H05K1/00 ,  H05K3/02

CPC classification number: H05K1/115 ,  B32B37/1292 ,  B32B38/10 ,  B32B2310/0843 ,  B32B2457/08 ,  G08B13/244 ,  H05K1/0366 ,  H05K1/0386 ,  H05K3/027 ,  H05K3/046 ,  H05K3/386 ,  H05K3/4046 ,  H05K3/4084 ,  H05K2201/0284 ,  H05K2201/0355 ,  H05K2201/0382 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0522 ,  H05K2203/1388 ,  H05K2203/1394 ,  H05K2203/1545 ,  Y10T29/49156

Abstract: A method for manufacturing a circuit board featuring conductive patterns, said method comprising the following steps of:i) affixing a conductive layer, such as a metal foil (3), to a substrate material (1) selectively, such that a part of the conductive layer, such as the metal foil (3), comprising desired areas (3a) for the final product and narrow areas (3c) between the final product's conducting areas, is affixed to the substrate material (1) by means of a bond (2), and removal-intended more extensive areas (3b) of the conductive layer, for example the metal foil (3), are left substantially unattached to the substrate material in such a way that the removable area (3b) is in attachment with the substrate material (1) by not more than its edge portion to be patterned in a subsequent step ii) and possibly by sites which preclude a release of the removable areas prior to a step iii); ii) patterning, by a removal of material, the conductive layer, such as the metal foil (3), from narrow gaps between the desired conducting areas (3a), and from an outer periphery of the area (3b) removable in a solid state, for establishing conductor patterns; iii) removing the removable areas (3b), not affixed to the substrate material (1), from the conductive layer, such as the metal foil (3), in a solid state after the conductive layer's edge area, which was removed from the removable area's outer periphery during the course of step ii), no longer holds the removable areas (3b) attached by their edges to the substrate material.

Abstract translation: 一种制造具有导电图案的电路板的方法，所述方法包括以下步骤：i）选择性地将诸如金属箔（3）的导电层固定到基底材料（1）上，使得部分 导电层，例如金属箔（3），其包含用于最终产品的所需区域（3a）和最终产品的导电区域之间的狭窄区域（3c），通过粘合剂（1）固定到基底材料（1） 导电层，例如金属箔（3）的移除目的更广泛的区域（3b）基本上不附着于基底材料，使得可移除区域（3b）与 基底材料（1）不超过其后续步骤ii）中待图案化的边缘部分，并且可能通过在步骤iii）之前排除可释放区域的释放的部位; ii）通过从所需导电区域（3a）之间的狭窄间隙和从固体可移除的区域（3b）的外周边去除导电层（例如金属箔（3））的图案， 状态，用于建立导体图案; iii）在导电层的边缘区域从固体状态除去导电层的边缘区域之后，从导电层（例如金属箔（3））上去除不附着于基底材料（1）的可移除区域（3b） 在步骤ii）的过程中，可移除区域的外围不再将其边缘附着的可移除区域（3b）保持在衬底材料上。

公开(公告)号：US20100328913A1

公开(公告)日：2010-12-30

申请号：US12791565

申请日：2010-06-01

Applicant: Andreas Kugler ,  Karl-Friederich Becker ,  Gerhard Liebing

Inventor： Andreas Kugler ,  Karl-Friederich Becker ,  Gerhard Liebing

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/10

CPC classification number: H05K1/188 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/1461 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/0272 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0355 ,  Y10T29/49146 ,  Y10T29/49155 ,  H01L2924/00

Abstract: In a method for producing an electronic subassembly, at least one electronic component is mounted on an insulating layer of a conductive foil in a first step, the active side of the electronic component pointing in the direction of the conductive foil. In a second step, the conductive foil having the at least one electronic component mounted thereon is laminated to a circuit board substrate, the at least one electronic component pointing in the direction of the circuit board substrate. Finally, circuit tracks are developed by patterning the conductive foil, and the at least one electronic component is contacted.

Abstract translation: 在一种电子组件的制造方法中，在第一步骤中，至少一个电子部件安装在导电箔的绝缘层上，电子部件的有源侧指向导电箔的方向。 在第二步骤中，将安装有至少一个电子部件的导电箔层压到电路板基板上，所述至少一个电子部件指向电路板基板的方向。 最后，通过图案化导电箔来开发电路轨迹，并且使至少一个电子部件接触。

公开(公告)号：US07856708B2

公开(公告)日：2010-12-28

申请号：US11532715

申请日：2006-09-18

Applicant: Eric Eckstein ,  Andre Cote

Inventor： Eric Eckstein ,  Andre Cote

IPC: H05K3/02

CPC classification number: B32B37/025 ,  B32B2310/0843 ,  B32B2519/02 ,  G08B13/2414 ,  G08B13/244 ,  H05K1/162 ,  H05K3/046 ,  H05K2201/0355 ,  H05K2201/09672 ,  H05K2203/0522 ,  H05K2203/0528 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T156/10 ,  Y10T156/1041 ,  Y10T156/1052 ,  Y10T156/1062 ,  Y10T156/1077 ,  Y10T156/108 ,  Y10T156/1082 ,  Y10T156/1089 ,  Y10T156/1097

Abstract: A process for forming a portion of a package or envelope bearing printed indicia, a label bearing printed indicia or a sheet bearing printed indicia includes providing a substrate which constitutes a portion of the package, label or sheet to a printing apparatus, and utilizing the printing apparatus or an adjunct to the printing apparatus to form at least one electrically conductive component of an EAS and/or RFID tag on the substrate substantially contemporaneously with the printing of the indicia on the substrate. The forming of the electrically conductive component on the substrate is accomplished slightly prior to the printing of the indicia on the substrate, slightly after the printing of the indicia on the substrate and at the same time as the printing of the indicia on the substrate.

Abstract translation: 用于形成承载印刷标记的包装或信封的一部分的方法，带有印刷标签的印刷标签或承载印刷标记的片材的方法包括将构成包装，标签或片材的一部分的基材提供到印刷装置，并且利用印刷 装置或辅助装置，以基本上同时在基板上印刷标记而在基板上形成EAS和/或RFID标签的至少一个导电部件。 导电组件在衬底上的形成在印刷衬底上的标记之前略微地完成，稍后在衬底上印刷标记之后，并且与衬底上的标记的印刷同时进行。

公开(公告)号：US07838776B2

公开(公告)日：2010-11-23

申请号：US12148271

申请日：2008-04-17

Applicant: John M. Lauffer ,  Voya R. Markovich ,  Michael Wozniak

Inventor： John M. Lauffer ,  Voya R. Markovich ,  Michael Wozniak

IPC: H05K1/03

CPC classification number: H01L21/4857 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K3/383 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09318 ,  H05K2203/0353 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T428/12556 ,  Y10T428/12993 ,  H01L2224/0401

Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided.

Abstract translation: 其中两个导电层（例如，电镀铜箔）被结合（例如层压）到电介质层的电路化衬底。 物理地结合到电介质的两个箔表面中的每一个是光滑的（例如，优选通过化学处理），并且在其上包括薄的有机层，而两个箔的外表面也是光滑的（例如，优选也使用化学处理 步）。 这些导电层中的一个可以用作接地或电压平面，而另一个可以用作具有多个单独信号线作为其一部分的信号平面。 还提供了使用这种电路化基板的电气组件和信息处理系统。

公开(公告)号：US20100291402A1

公开(公告)日：2010-11-18

申请号：US12846865

申请日：2010-07-30

Applicant: Takemi Muroga ,  Yasuyuki Ito ,  Koji Aoyagi ,  Yoshiki Yamamoto ,  Kenji Yokomizo ,  Katsumi Nomura

Inventor： Takemi Muroga ,  Yasuyuki Ito ,  Koji Aoyagi ,  Yoshiki Yamamoto ,  Kenji Yokomizo ,  Katsumi Nomura

IPC: B32B15/20

CPC classification number: H05K1/09 ,  C22C9/02 ,  C22F1/08 ,  H05K1/0393 ,  H05K2201/0355 ,  H05K2203/0143 ,  H05K2203/1105 ,  Y10T428/12431

Abstract: A rolled copper foil applied with a recrystallization annealing after a final cold rolling step and having a crystal grain alignment satisfying a ratio of [a]/[b]≧3, where [a] and [b] are normalized average intensities of a {111}Cu plane diffraction of a copper crystal by β-scanning at α=35° and 74°, respectively, in an X-ray diffraction pole figure measurement to a rolled surface is manufactured by controlling a total working ratio in the final cold rolling step before the recrystallization annealing to be 94% or more; and controlling a working ratio per one pass in the final cold rolling step to be 15 to 50%.

Abstract translation: 在最终冷轧步骤之后进行再结晶退火并且具有满足[a] / [b]≥3的比例的晶粒取向的轧制铜箔，其中[a]和[b]是{ 111}在X射线衍射极数测量中，通过在最终冷中控制总的工作比来制造在α= 35°和74°的铜晶体的Cu平面衍射 再结晶退火前的轧制步骤为94％以上; 并且在最终冷轧步骤中将每一道次的加工率控制为15〜50％。

公开(公告)号：US20100261033A1

公开(公告)日：2010-10-14

申请号：US12738995

申请日：2009-05-29

Applicant: Terumasa Moriyama ,  Kengo Kaminaga

Inventor： Terumasa Moriyama ,  Kengo Kaminaga

IPC: H05K3/38 ,  C25D1/04

CPC classification number: H05K3/384 ,  C23C28/00 ,  C23C28/321 ,  C23C28/345 ,  C23C28/3455 ,  C25D3/562 ,  C25D3/565 ,  C25D7/0614 ,  H05K2201/0239 ,  H05K2201/0355 ,  H05K2203/0723 ,  Y10T428/12438 ,  Y10T428/12472 ,  Y10T428/12569 ,  Y10T428/12583 ,  Y10T428/1259 ,  Y10T428/12618 ,  Y10T428/1266 ,  Y10T428/12792 ,  Y10T428/12847 ,  Y10T428/12903 ,  Y10T428/12944 ,  Y10T428/263 ,  Y10T428/27 ,  Y10T428/273

Abstract: Provided is a copper foil for a printed circuit board comprising a layer including nickel, zinc, a compound of nickel and that of zinc (hereinafter referred to a “nickel zinc layer”) on a roughened surface of a copper foil, and a chromate film layer on the nickel zinc layer, wherein the zinc add-on weight per unit area of the nickel zinc layer is 180 μg/dm2 or more and 3500 μg/dm2 or less, and the nickel weight ratio in the nickel zinc layer {nickel add-on weight/(nickel add-on weight+zinc add-on weight)} is 0.38 or more and 0.7 or less. This surface treatment technology of a copper foil is able to effectively prevent the circuit corrosion phenomenon in cases of laminating a copper foil on a resin base material and using a sulfuric acid hydrogen peroxide etching solution to perform soft etching to the circuit.

Abstract translation: 提供一种用于印刷电路板的铜箔，其包括在铜箔的粗糙表面上包含镍，锌，镍化合物和锌的层（以下称为“镍锌层”）的层，以及铬酸盐膜 镍锌层的单位面积锌添加量为180μg/ dm 2以上且3500μg/ dm 2以下，镍锌层中的镍重量比（镍添加量） - 重量/（镍附加重量+锌附加重量）}为0.38以上且0.7以下。 铜箔的表面处理技术能够有效地防止在树脂基材上层叠铜箔并使用硫酸过氧化氢蚀刻溶液对电路进行软蚀刻的情况下的电路腐蚀现象。

公开(公告)号：US20100202114A1

公开(公告)日：2010-08-12

申请号：US12699628

申请日：2010-02-03

Applicant: Risto Tuominen ,  Petteri Palm

Inventor： Risto Tuominen ,  Petteri Palm

IPC: H05K7/00

CPC classification number: H01L23/5389 ,  H01L23/5385 ,  H01L23/544 ,  H01L23/552 ,  H01L24/19 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0652 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/7565 ,  H01L2224/7665 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/188 ,  H05K3/025 ,  H05K3/4611 ,  H05K2201/0355 ,  H01L2924/00

Abstract: An electronic module, comprising: a conductive-pattern layer; an insulating-material layer supporting the conductive-pattern layer; at least one component inside the insulating-material layer, the at least one component comprising a first surface and contact zones on the first surface; a first hardened adhesive layer on the first surface of the at least one component; a second hardened adhesive layer in contact with the conductive-pattern layer and the first hardened adhesive layer; holes in the first and second hardened adhesive layer at the locations of the contact zones; and conductive material in the holes and in electrical connection with the contact zones of the component and the conductive-pattern layer.

Abstract translation: 一种电子模块，包括：导电图案层; 支撑导电图案层的绝缘材料层; 所述绝缘材料层内的至少一个部件，所述至少一个部件包括第一表面和所述第一表面上的接触区域; 在所述至少一个部件的第一表面上的第一硬化粘合剂层; 与导电图案层和第一硬化粘合剂层接触的第二硬化粘合剂层; 在接触区的位置处的第一和第二硬化粘合剂层中的孔; 和孔中的导电材料，并与元件和导电图案层的接触区电连接。

公开(公告)号：US20100175914A1

公开(公告)日：2010-07-15

申请号：US12352411

申请日：2009-01-12

Applicant: Pranabes K. PRAMANIK ,  Yuji KAGEYAMA ,  Fujio KUWAKO ,  Jin Hyun HWANG

Inventor： Pranabes K. PRAMANIK ,  Yuji KAGEYAMA ,  Fujio KUWAKO ,  Jin Hyun HWANG

IPC: H05K1/03 ,  B31B1/60 ,  H01G4/06

CPC classification number: H01G4/18 ,  H01G4/203 ,  H01G4/33 ,  H05K1/162 ,  H05K2201/0166 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09309 ,  Y10T156/10

Abstract: A thin laminate passive electrical device, such as, a capacitor, and a method of fabricating a thin laminate passive electrical device are provided. The passive electrical device includes two conductors, for example, copper foil conductors, separated by a dielectric having a first layer of a first material having a softening point temperature greater than a first temperature and a first layer of a second material having a softening point temperature less than the first temperature. The first temperature may be at least 150 degrees C. or higher. By providing a first layer having a higher softening point material, shorting across the conductors, that can be promoted by the fabrication process, is prevented. Methods of fabricating passive electrical devices are also disclosed.

Abstract translation: 提供了一种诸如电容器的薄层压无源电器件以及制造薄层压无源电器件的方法。 无源电器件包括两个导体，例如铜箔导体，由具有软化点温度大于第一温度的第一材料的第一层和第一材料的电介质隔开，第一层的第一材料具有软化点温度 小于第一温度。 第一温度可以为至少150摄氏度或更高。 通过提供具有较高软化点材料的第一层，可以防止通过制造工艺促进导体的短路。 还公开了制造无源电器件的方法。

公开(公告)号：US07737818B2

公开(公告)日：2010-06-15

申请号：US11891067

申请日：2007-08-08

Applicant: Aleksandra Djordjevic ,  Carl W. Berlin

Inventor： Aleksandra Djordjevic ,  Carl W. Berlin

IPC: H01C1/012

CPC classification number: H05K1/16 ,  H01C7/003 ,  H01C13/02 ,  H01G4/33 ,  H01G4/40 ,  H05K1/092 ,  H05K1/162 ,  H05K1/167 ,  H05K3/1291 ,  H05K2201/0355 ,  H05K2201/1053 ,  H05K2203/1126

Abstract: An embedded resistor and capacitor circuit and fabrication method is provided. The circuit includes a substrate, a conductive foil laminated to the substrate, and a thick film dielectric material disposed on the conductive foil. One or more thick film electrodes are formed on the dielectric material and a thick film resistor is formed at least partially contacting the thick film electrodes. A capacitor is formed by an electrode and the conductive foil. The electrodes serve as terminations for the resistor and capacitor.

Abstract translation: 提供了一种嵌入式电阻和电容电路及其制造方法。 电路包括基板，层叠在基板上的导电箔，以及设置在导电箔上的厚膜电介质材料。 在电介质材料上形成一个或多个厚膜电极，并且形成至少部分地接触厚膜电极的厚膜电阻器。 电极由电极和导电箔形成。 电极用作电阻器和电容器的端子。

公开(公告)号：US07733626B2

公开(公告)日：2010-06-08

申请号：US11891443

申请日：2007-08-10

Applicant: Cengiz A. Palanduz ,  Yongki Min

Inventor： Cengiz A. Palanduz ,  Yongki Min

IPC: H01G4/008 ,  H01G4/06

CPC classification number: H01G4/12 ,  H01L2224/16225 ,  H05K1/0313 ,  H05K1/092 ,  H05K1/162 ,  H05K2201/017 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/1131 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49155

Abstract: A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive material on the ceramic material; and sintering the ceramic material. A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive material on the ceramic material so that the ceramic material is disposed between the first conductive material and the second conductive material; thermal processing at a temperature sufficient to sinter the ceramic material and form a film of the second conductive material; and coating an exposed surface of at least one of the first conduct material and the second conductive material with a different conductive material. An apparatus including first and second electrodes; and a ceramic material between the first electrode and the second electrode, wherein the ceramic material is sintered directly on one of the first and second electrode.

Abstract translation: 一种包括在第一导电材料的片材上直接形成陶瓷材料的方法; 在所述陶瓷材料上形成第二导电材料; 并烧结陶瓷材料。 一种包括在第一导电材料的片材上直接形成陶瓷材料的方法; 在所述陶瓷材料上形成第二导电材料，使得所述陶瓷材料设置在所述第一导电材料和所述第二导电材料之间; 在足以烧结陶瓷材料并形成第二导电材料的膜的温度下进行热处理; 以及用不同的导电材料涂覆第一导电材料和第二导电材料中的至少一个的暴露表面。 一种包括第一和第二电极的装置; 以及在第一电极和第二电极之间的陶瓷材料，其中陶瓷材料直接烧结在第一和第二电极之一上。