公开(公告)号：US4919970A

公开(公告)日：1990-04-24

申请号：US907265

申请日：1986-09-15

Applicant: Karl G. Hoebener ,  John J. Stankus

Inventor： Karl G. Hoebener ,  John J. Stankus

IPC: B23K3/06 ,  H05K3/12 ,  H05K3/34

CPC classification number: H05K3/1233 ,  H05K3/12 ,  H05K2201/09572 ,  H05K2203/0139 ,  H05K2203/163

Abstract: A technique for one step solder application through a mask to a printed circuit board (PCB) having pads for surface mountable components and through holes for a leaded components is disclosed wherein the amount of solder deposited on the pads and in the holes is simultaneously, independently controlled as a function of mask thickness, blade hardness and blade to mask angle.

公开(公告)号：US4377316A

公开(公告)日：1983-03-22

申请号：US238873

申请日：1981-02-27

Applicant: Mario E. Ecker ,  Leonard T. Olson

Inventor： Mario E. Ecker ,  Leonard T. Olson

IPC: H01L23/32 ,  H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K3/30 ,  H05K3/34 ,  H05K3/36 ,  H05K1/18

CPC classification number: H05K3/303 ,  H01L21/486 ,  H01L23/4985 ,  H01L23/5384 ,  H05K3/363 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/16152 ,  H05K1/0206 ,  H05K1/113 ,  H05K1/141 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/10659 ,  H05K2201/10666 ,  H05K2201/10681 ,  H05K2201/10727 ,  H05K2201/10878 ,  H05K2201/2036 ,  H05K2203/043 ,  H05K3/308 ,  H05K3/3447 ,  H05K3/3452 ,  H05K3/3457 ,  Y02P70/613

Abstract: A system for connecting a semiconductor chip carrier to a printed circuit card is described. The semiconductor chip carrier has a flexible, extendable wiring membrane attached to the bottom thereof which extends beyond the periphery of the semiconductor chip carrier and in the area beyond the periphery is provided with electrical contacts. The electrical contacts are mated to complementary contacts in a printed circuit card which is biased from the semiconductor chip carrier by electrical and thermal contact means. The membrane, inter alia, provides high density electrical contact between the semiconductor and printed circuit card. Various elements thereof and a process for forming the same are described.

Abstract translation: 描述了用于将半导体芯片载体连接到印刷电路卡的系统。 半导体芯片载体具有附接到其底部的柔性的可延伸的布线膜，其延伸超出半导体芯片载体的周边，并且在超过外围的区域中设置有电触点。 电触点与印刷电路卡中的互补触点配合，印刷电路卡通过电接触和热接触装置从半导体芯片载体偏置。 该膜尤其在半导体和印刷电路卡之间提供了高密度的电接触。 对其各种要素及其形成方法进行说明。

公开(公告)号：US20240314943A1

公开(公告)日：2024-09-19

申请号：US18576236

申请日：2021-12-20

Applicant: Mitsubishi Electric Corporation

Inventor： Hiromitsu ITAMOTO

IPC: H05K3/46 ,  H05K1/14 ,  H05K3/36

CPC classification number: H05K3/4691 ,  H05K1/144 ,  H05K1/147 ,  H05K3/363 ,  H05K2201/09572

Abstract: Solder (12) joins together a second conductive pattern (4) of a flexible substrate (1) and a third conductive pattern (7) of a print substrate (6) and joins together a second GND pattern (5) of the flexible substrate (1) and a third GND pattern (8) of the print substrate (6). A through hole (11) passes through the flexible substrate (1) and connects the first and second GND patterns (3,5) together. In an extension direction in which the second conductive pattern (4) extends, an end portion of a solder joint portion between the second conductive pattern (4) and the third conductive pattern (7) is in a position corresponding to the through hole (11) and is shifted from an end portion of the through hole (11).

公开(公告)号：US20240260168A1

公开(公告)日：2024-08-01

申请号：US18565359

申请日：2022-06-08

Applicant: VITESCO TECHNOLOGIES GMBH

Inventor： Detlev Bagung ,  Christina QUEST-MATT ,  Holger BALDREICH

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K1/0206 ,  H05K3/0094 ,  H05K3/341 ,  H05K2201/09545 ,  H05K2201/09572 ,  H05K2201/09609

Abstract: A circuit board (1) for a power semiconductor module (13), having at least one top side (2) and one bottom side (3), wherein at least one mounting area (4) for a power semiconductor component (12) is provided on the top side (2), wherein on the mounting area (4), at least one solder layer (8) is provided for connecting at least one power semiconductor component (12) to the mounting area (4), which layer is divided into regions (9) that are separated from one another by means of intermediate spaces (11), and wherein multiple thermal vias (5) are provided in the circuit board (1) and extend from the top side (2) to the bottom side (3) of the circuit board (2) in the region of the mounting area (4), wherein each upper opening (6) of the thermal vias (5) is directly surrounded by a respective region (9) of the solder layer (8) and each lower opening (7) of the vias (5) is covered by a layer (10) of electrically insulating material.

公开(公告)号：US20190008044A1

公开(公告)日：2019-01-03

申请号：US15635201

申请日：2017-06-28

Applicant: Sierra Circuits, Inc.

Inventor： Konstantine KARAVAKIS ,  Kenneth S. BAHL

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/18 ,  H05K3/06 ,  H05K1/03 ,  H05K1/09 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K1/0313 ,  H05K1/095 ,  H05K1/111 ,  H05K3/06 ,  H05K3/181 ,  H05K3/425 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/09572 ,  H05K2201/10378 ,  H05K2203/068 ,  H05K2203/085

Abstract: A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.

公开(公告)号：US09839128B2

公开(公告)日：2017-12-05

申请号：US15220771

申请日：2016-07-27

Applicant: International Business Machines Corporation

Inventor： Phillip D. Isaacs

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/18 ,  H05K3/42 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34

CPC classification number: H05K1/181 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/0209 ,  H05K1/0215 ,  H05K1/114 ,  H05K1/116 ,  H05K3/3431 ,  H05K3/3436 ,  H05K3/429 ,  H05K2201/09572 ,  H05K2201/10727 ,  H05K2201/10969 ,  H05K2203/0207 ,  H05K2203/176 ,  Y10T29/49144

Abstract: An apparatus includes a printed circuit board. The printed circuit board includes at least one conductive layer on top a first dielectric layer, wherein the at least one conductive layer comprises at least one of a ground plane and a power plane. The printed circuit board includes a second dielectric layer on top of the at least one conductive layer. The printed circuit board includes a thermal pad on top of the second dielectric layer. The printed circuit board is fabricated by forming at least one plated through hole for electrically coupling the thermal pad to the at least one conductive layer. The printed circuit board is fabricated by backdrilling the at least one plated through hole to remove a portion of the conductive material, wherein subsequent to the backdrilling the conductive material remaining in the at least one plated through hole electrically couples one or more of the at least one conductive layer to the thermal pad.

公开(公告)号：US09629241B2

公开(公告)日：2017-04-18

申请号：US14571621

申请日：2014-12-16

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yue Wu

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/34

CPC classification number: H05K1/113 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/10734 ,  Y02P70/613

Abstract: A printed circuit board, a ball grid array package and a wiring method of a printed circuit board are provided. The printed circuit board comprises: a substrate, the substrate including a plurality of insulating layers stacked and a plurality of conductive layers disposed between adjacent insulating layers; a plurality of pads, disposed in a two-dimensional matrix on a surface of the substrate; and a plurality of via holes, disposed corresponding to each pad and running through the substrate and the corresponding pad. The ball grid array package according to an embodiment of the invention comprises the above-described printed circuit board.

公开(公告)号：US20160360613A1

公开(公告)日：2016-12-08

申请号：US15173408

申请日：2016-06-03

Applicant: Samuel P. Kho

Inventor： Samuel P. Kho

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/00 ,  H05K1/11 ,  H05K3/40

CPC classification number: H05K1/0289 ,  H05K1/0215 ,  H05K1/0269 ,  H05K1/0286 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0293 ,  H05K1/09 ,  H05K1/11 ,  H05K3/1216 ,  H05K2201/0305 ,  H05K2201/09254 ,  H05K2201/09563 ,  H05K2201/09572 ,  H05K2201/09609 ,  H05K2203/166

Abstract: The present invention relates generally to electric circuit testing, building, or implementing using a breadboard style PCB. Aspects of the present invention include eliminating the need to use hookup wires when building and testing electric circuits on PCBs. In embodiments, a PCB system having rows and columns of signal tie points connected in a breadboard layout and using an embedded wire and a solder bridge to form partial connections between signal tie points. In embodiments, the embedded wire and solder bridge is capable of connecting a column of signal tie points. In embodiments, the embedded wire and solder bridge is capable of connecting a power rail to a signal tie point. Thus, a circuit can be implemented and tested by applying a small amount of solder to the solder bridge without the need for hookup wires.

Abstract translation: 本发明一般涉及使用面包板式PCB的电路测试，构建或实现。 本发明的方面包括在PCB上构建和测试电路时消除了使用连接线的需要。 在实施例中，PCB系统具有以面包板布局连接的信号连接点的行和列，并且使用嵌入的线和焊接桥来形成信号连接点之间的部分连接。 在实施例中，嵌入式线和焊接桥能够连接一列信号连接点。 在实施例中，嵌入式线和焊接桥能够将电力轨连接到信号连接点。 因此，可以通过在焊料桥上施加少量焊料来实现和测试电路，而不需要连接线。

公开(公告)号：US09462703B2

公开(公告)日：2016-10-04

申请号：US14044135

申请日：2013-10-02

Applicant: International Business Machines Corporation

Inventor： Phillip D. Isaacs

IPC: H01K3/10 ,  H05K3/42 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K1/181 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/0209 ,  H05K1/0215 ,  H05K1/114 ,  H05K1/116 ,  H05K3/3431 ,  H05K3/3436 ,  H05K3/429 ,  H05K2201/09572 ,  H05K2201/10727 ,  H05K2201/10969 ,  H05K2203/0207 ,  H05K2203/176 ,  Y10T29/49144

Abstract: A method includes fabricating a printed circuit board. The fabricating includes forming at least one conductive layer on top a first dielectric layer, wherein the at least one conductive layer comprises at least one of a ground plane and a power plane. The fabricating includes forming a second dielectric layer on top of the at least one conductive layer. The fabricating includes forming a thermal pad on top of the second dielectric layer. The fabricating includes forming at least one plated through hole for electrically coupling the thermal pad to the at least one conductive layer. The fabricating includes backdrilling the at least one plated through hole to remove a portion of the conductive material, wherein subsequent to the backdrilling the conductive material remaining in the at least one plated through hole electrically couples one or more of the at least one conductive layer to the thermal pad.

Abstract translation: 一种方法包括制造印刷电路板。 该制造包括在第一介电层的顶部上形成至少一个导电层，其中至少一个导电层包括接地层和电源层中的至少一个。 该制造包括在至少一个导电层的顶部上形成第二电介质层。 该制造包括在第二介电层的顶部上形成热垫。 该制造包括形成至少一个电镀通孔，用于将热垫电耦合到至少一个导电层。 所述制造包括对所述至少一个电镀通孔进行后钻，以去除所述导电材料的一部分，其中在所述回钻之后，残留在所述至少一个电镀通孔中的所述导电材料将所述至少一个导电层中的一个或多个电耦合到 散热垫。

公开(公告)号：US09437566B2

公开(公告)日：2016-09-06

申请号：US14275514

申请日：2014-05-12

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L21/44 ,  H01L23/00 ,  H05K3/34 ,  H05K1/11 ,  H05K1/14 ,  B23K26/32 ,  B23K3/06 ,  B23K35/02 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L21/02 ,  B23K1/00

CPC classification number: H01L24/14 ,  B23K1/0016 ,  B23K3/0623 ,  B23K35/0244 ,  B23K35/0266 ,  B23K2101/40 ,  H01L21/02225 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/98 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/0333 ,  H01L2224/0391 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/051 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/06102 ,  H01L2224/10145 ,  H01L2224/11001 ,  H01L2224/11005 ,  H01L2224/11009 ,  H01L2224/111 ,  H01L2224/11318 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/1405 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75253 ,  H01L2224/81138 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8122 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/115 ,  H05K1/144 ,  H05K3/341 ,  H05K2201/09572 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2224/81 ,  H01L2224/83

Abstract: In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.

Abstract translation: 在一些实施例中，为了增加将不同结构与一个或多个焊球连接的焊料连接的高度与间距比，当连接形成在一个结构上时和/或当 连接正在附加到另一个结构。 在一些实施例中，非焊球通过中间焊球（140i）连接。 焊料连接可以被焊料锁定层（1210）包围，并且可以凹陷在该层中的孔（1230）中。 还提供其他功能。