公开(公告)号：US20170098026A1

公开(公告)日：2017-04-06

申请号：US14872989

申请日：2015-10-01

Applicant: Altera Corporation

Inventor： Chee Yong Ew

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F9/4403 ,  G06F15/7871 ,  G06F17/505 ,  G06F2217/66

Abstract: Methods for control block size reduction of a controller of an integrated circuit (IC) device through intellectual property (IP) migration in the IC device are disclosed. A disclosed method includes receiving configuration data for the IC device and determining whether IP construction data is defined in the configuration data. The IP construction data contains instruction sets for implementing logical operations of a controller-based IP core in a core region of the IC device. Such data creates flexibility to configure the controller-based IP core in a core logic circuit as a soft IP core, when required. In this scenario, the controller-based IP core can be removed from the controller of the IC device during IC device fabrication. As a result, the footprint (e.g., area) of the controller of the IC device can be reduced, which subsequently increases cost-savings for the IC device fabrication.

公开(公告)号：US09613232B1

公开(公告)日：2017-04-04

申请号：US14880633

申请日：2015-10-12

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F7/44 ,  G06G7/16 ,  G06G7/14

CPC classification number: G06G7/16 ,  G06F7/44 ,  G06F7/483 ,  G06F7/52 ,  G06F7/5443 ,  G06G7/14 ,  H03H17/06 ,  H03H2220/04 ,  H03H2220/06

Abstract: A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of vector (dot product) operations, FIR filters, or sum-of-product operations.

公开(公告)号：US09602587B2

公开(公告)日：2017-03-21

申请号：US14316400

申请日：2014-06-26

Applicant: Altera Corporation

Inventor： Dana How

IPC: G06F15/16 ,  H04L29/08 ,  H04L12/721

CPC classification number: H04L67/10 ,  H04L45/06

Abstract: Systems and methods are provided herein for implementing a Network-on-Chip (NoC) in a System-on-Chip (SoC) device. In some embodiments, an NoC may include a first node that transmits data to a second node, where data may be transmitted via either a first plane or a second plane. The first plane may utilize first logic at each of an output port of the first node, an input port of the second node, and at intermediary ports when transmitting the data to the second node. The second plane may utilize first logic at the output port of the first node and at the input port of the second node when transmitting the data to the second node, and may utilize second logic that is different from the first logic at the intermediary ports when transmitting the data to the second node.

公开(公告)号：US09602106B1

公开(公告)日：2017-03-21

申请号：US14639735

申请日：2015-03-05

Applicant: Altera Corporation

Inventor： Mark Bourgeault

IPC: H03H11/26 ,  G06F1/04 ,  H03K19/173 ,  H03K3/037 ,  H03L7/10 ,  G06F17/50

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F17/5027 ,  G06F17/5031 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H03K3/0375 ,  H03K19/1733 ,  H03L7/07

Abstract: An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

公开(公告)号：US09601419B1

公开(公告)日：2017-03-21

申请号：US14298230

申请日：2014-06-06

Applicant: Altera Corporation

Inventor： Teik Tiong Toong ,  Chong Poh Lim

IPC: H01L23/48 ,  H01L23/495 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L23/49531 ,  H01L23/49541 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A multi-package unit having stacked packages is provided. A multi-package unit may include a first package and a second package mounted on the first package. The first package may be a leadframe package that includes metal leads extending beyond the perimeter of the first package. The first package may include a first integrated circuit die assembled within the first package using the wirebond configuration or the flip-chip configuration. The second package may be a leadframe package or a leadless package that includes a second integrated circuit die. The second package may be smaller than the first package. The first and second integrated circuit dies may be formed using different integrated circuit fabrication technologies.

公开(公告)号：US09600278B1

公开(公告)日：2017-03-21

申请号：US13941847

申请日：2013-07-15

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F7/483 ,  G06F9/30

CPC classification number: G06F9/3001 ,  G06F7/483 ,  G06F7/509 ,  G06F7/5443 ,  H03K19/17732 ,  H03K19/17744

Abstract: A specialized processing block on a programmable integrated circuit device includes a first floating-point arithmetic operator stage, and a floating-point adder stage having at least one floating-point binary adder. Configurable interconnect within the specialized processing block routes signals into and out of each of the first floating-point arithmetic operator stage and the floating-point adder stage. The block has a plurality of block inputs, at least one block output, a direct-connect input for connection to a first other instance of the specialized processing block, and a direct-connect output for connection to a second other instance of the specialized processing block. A plurality of instances of the specialized processing block are together configurable as a binary or ternary recursive adder tree.

公开(公告)号：US09596160B1

公开(公告)日：2017-03-14

申请号：US14529912

申请日：2014-10-31

Applicant: ALTERA CORPORATION

Inventor： Peng Li ,  Masashi Shimanouchi ,  Hsinho Wu

IPC: H04L12/26

CPC classification number: H04L43/087 ,  H04L1/205

Abstract: One embodiment of the present invention relates to a method for built-in self-measurement (BISM) of jitter components. A built-in self-measurement controller on the host integrated circuit (and, in some cases, a slave controller on a partner integrated circuit) may be used to control various switches to form various loopback circuits. A calibrated jittery data pattern is transmitted through each of the various loopback circuits. On-die instrumentation (ODI) circuitry may then be used to measure intrinsic jitter components for each loopback circuit via data representations such as eye-diagrams, or jitter histograms, or bit error ratio bathtub curves. The intrinsic jitter for link components (i.e. the jitter components such as deterministic jitter (DJ), random jitter (RJ), total jitter (TJ)) may then be determined based on the measured intrinsic jitters for the various loopback circuits. Other embodiments and features are also disclosed.

Abstract translation: 本发明的一个实施例涉及一种用于抖动分量的内置自测量（BISM）的方法。 可以使用主机集成电路（以及在某些情况下，伙伴集成电路上的从控制器）上的内置自测量控制器来控制各种开关以形成各种环回电路。 校准的抖动数据模式通过各个环回电路中的每一个发送。 然后可以使用管芯仪表（ODI）电路来通过数据表示（例如眼图或抖动直方图）或误码率浴缸曲线来测量每个环回电路的固有抖动分量。 然后可以基于所测量的各种环回电路的本征抖动来确定链路组件的固有抖动（即抖动分量，例如确定性抖动（DJ），随机抖动（RJ），总抖动（TJ））。 还公开了其它实施例和特征。

公开(公告)号：US20170068765A1

公开(公告)日：2017-03-09

申请号：US14846645

申请日：2015-09-04

Applicant: Altera Corporation

Inventor： Nishanth Sinnadurai ,  Gordon Raymond Chiu

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2217/84

Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design. For example, the circuit design computing equipment may preserve the register retiming solution from the first circuit design implementation for portions of the second circuit design that are outside the region-of-change and incrementally create graphs that allow to incrementally solve the register retiming problem during the second circuit design implementation.

Abstract translation: 第一电路设计描述可以具有寄存器和组合门。 电路设计计算设备可以在第一电路设计描述上执行寄存器重新定时，由此在第一电路设计实现期间寄存器移动到组合门上。 第一电路设计的工程改变顺序（ECO）可能导致第二电路设计。 第一和第二电路设计之间的差异可以局限于变化的区域。 电路设计计算设备可以保留来自第一电路设计实现的结果，并且在实施第二电路设计期间重新使用这些结果的部分。 例如，电路设计计算设备可以保留来自第一电路设计实现的寄存器重新定时解决方案，用于在变化范围之外的第二电路设计的部分，并且增量地创建允许递增地解决寄存器重定时问题的图形 第二电路设计实现。

公开(公告)号：US09589612B1

公开(公告)日：2017-03-07

申请号：US14602131

申请日：2015-01-21

Applicant: ALTERA CORPORATION

Inventor： Arifur Rahman ,  Bernhard Friebe

IPC: H03K19/003 ,  G11C7/22 ,  G06F1/00 ,  H03K19/00

CPC classification number: G06F13/1689 ,  G06F1/00 ,  G06F13/4068 ,  G06F13/42 ,  G11C7/22 ,  G11C8/00 ,  G11C29/12 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H03K19/00 ,  H03K19/003 ,  H03K19/1733 ,  H03K19/1776

Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

Abstract translation: 提供了系统和方法来增强集成电路的功能。 这种集成电路可以包括主要电路和可编程的用于调整主电路的功能的嵌入式可编程逻辑。 具体地，嵌入式可编程逻辑可以被编程为调整主电路的功能以补充和/或支持另一集成电路的功能。 因此，嵌入式可编程逻辑可以用诸如数据/地址操作功能，配置/测试功能，计算功能等的功能进行编程。

公开(公告)号：US20170061162A1

公开(公告)日：2017-03-02

申请号：US14830171

申请日：2015-08-19

Applicant: Altera Corporation

Inventor： Robert Groza

IPC: G06F21/72 ,  G06F21/76

CPC classification number: G06F21/72 ,  G06F21/76 ,  G09C1/00 ,  H04L9/0637 ,  H04L2209/12 ,  H04L2209/122 ,  H04L2209/125

Abstract: Systems and methods are discussed herein for reusing hardware for encryption and authentication, where the hardware has a fixed input bandwidth, and where the hardware has the same bandwidth for a different input bandwidth. In order to accomplish this mechanism, systems and methods are provided herein for processing invalid data that appears within streams of valid data. Systems and methods are also provided herein for authentication mechanisms that require more than one data cycle to complete.

Abstract translation: 本文将讨论用于重新使用硬件进行加密和认证的系统和方法，其中硬件具有固定的输入带宽，并且硬件对于不同的输入带宽具有相同的带宽。 为了实现这一机制，本文提供了用于处理出现在有效数据流内的无效数据的系统和方法。 本文还提供了需要多于一个数据周期来完成的认证机制的系统和方法。