公开(公告)号：US06940524B2

公开(公告)日：2005-09-06

申请号：US10409131

申请日：2003-04-09

Applicant: Wen-Kuo Lin

Inventor： Wen-Kuo Lin

IPC: G06T5/00 ,  G09G5/00

CPC classification number: G06T5/002 ,  G06T5/003 ,  G06T5/009 ,  G06T5/20

Abstract: A method for adjusting sharpness and brightness of a digital image. In this method, an image function is first inputted into a processor. The image function comprises a plurality of control parameters. Next, the control parameter values of the control parameters are set, and then each of the pixels is sequentially leaded into the image function according to the control parameter value so as to perform the corresponding operation for adjusting the sharpness and brightness of the image. Finally, the adjusted image is outputted. Therefore, the two processes in the prior art, one for adjusting the brightness, the other for the sharpness, are merged into one process so that the design of the hardware circuit is simplified and the required memory space is reduced.

Abstract translation: 一种用于调整数字图像的清晰度和亮度的方法。 在该方法中，首先将图像功能输入到处理器中。 图像功能包括多个控制参数。 接下来，设置控制参数的控制参数值，然后根据控制参数值将每个像素依次引导到图像功能中，以执行用于调整图像的清晰度和亮度的相应操作。 最后，输出调整后的图像。 因此，现有技术中的两个处理，一个用于调整亮度，另一个用于清晰度，被合并成一个过程，从而简化了硬件电路的设计并减少了所需的存储空间。

公开(公告)号：US06868130B2

公开(公告)日：2005-03-15

申请号：US09840987

申请日：2001-04-25

Applicant: Tsung-Lin Lee

Inventor： Tsung-Lin Lee

IPC: H04L25/06 ,  H04L27/26 ,  H04L27/16

CPC classification number: H04L25/069 ,  H04L27/2647

Abstract: A transmission mode detector for digital receiver is proposed. The transmission mode detector comprises a RF tuner for receiving RF signals and generating intermediate frequency (IF) signals. An envelope detector is employed to filter the IF signals and generate rough envelope signal and a hard-decision machine is employed to quantize the rough envelope signal into hard-decision binary signals. The transmission mode detector further comprises a glitch remover to remove the unwanted glitch in the binary signals and generate envelope signal. An A/D converter is used to quantize the IF signals and generate digital signal. Further more, an I/Q de-multiplexer is used to extract the in-phase and the quadrature terms of the OFDM symbol from the digital signal. The transmission mode detector then detects the transmission mode by a mode detect unit according to the period of the envelope signal. If the detected mode is mode II or III, then the mode detect unit further distinguishes the transmission mode based on the auto-correlations of the OFDM symbol.

Abstract translation: 提出了一种数字接收机的传输模式检测器。 传输模式检测器包括用于接收RF信号并产生中频（IF）信号的RF调谐器。 采用包络检波器对IF信号进行滤波并产生粗糙包络信号，采用硬判决机将粗糙包络信号量化为硬决策二进制信号。 传输模式检测器还包括毛刺去除器以去除二进制信号中的不需要的毛刺并产生包络信号。 A / D转换器用于量化IF信号并产生数字信号。 此外，使用I / Q解复用器从数字信号中提取OFDM符号的同相和正交项。 传输模式检测器然后根据包络信号的周期通过模式检测单元检测传输模式。 如果检测模式是模式II或III，则模式检测单元进一步基于OFDM符号的自相关来区分传输模式。

公开(公告)号：US06864586B2

公开(公告)日：2005-03-08

申请号：US10375079

申请日：2003-02-28

Applicant: Han-Kun Hsieh ,  Wei-Feng Lin

Inventor： Han-Kun Hsieh ,  Wei-Feng Lin

IPC: H05K1/11 ,  H05K3/24 ,  H05K3/34 ,  H05K3/40 ,  H01L23/48

CPC classification number: H05K3/243 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/0571 ,  H05K2203/072 ,  H05K2203/0723 ,  H01L2924/00

Abstract: A padless high density circuit board and manufacturing method thereof. The method includes providing a circuit board substrate, forming external wiring, having a plurality of external terminals with a width as large as or less than the external wiring on the circuit board substrate, forming a solder mask over the circuit board substrate and the external wiring with a plurality of solder mask openings exposing the external terminals, with diameters at least as large as the widths of the external terminals exposed thereby, and forming a plurality of conductive bumps on the external terminals exposed by the solder mask openings for connection with an external device in a subsequent assembly process.

Abstract translation: 一种无衬垫高密度电路板及其制造方法。 该方法包括提供电路板基板，形成外部布线，具有宽度大于或小于电路板基板上的外部布线的多个外部端子，在电路板基板和外部布线上形成焊料掩模 具有暴露外部端子的多个焊接掩模开口，其直径至少​​与由此暴露的外部端子的宽度一样大，并且在由焊接掩模开口暴露的外部端子上形成多个导电凸块，用于与外部 设备在随后的组装过程中。

公开(公告)号：US06864150B2

公开(公告)日：2005-03-08

申请号：US10384287

申请日：2003-03-06

Applicant: Ping-Wei Lin ,  Gwo-Chyuan Kuoh ,  Chao-Sheng Chiang

Inventor： Ping-Wei Lin ,  Gwo-Chyuan Kuoh ,  Chao-Sheng Chiang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76232

Abstract: The present invention disclosed a manufacturing method of shallow trench isolation (STI). By making use of depositing two layer of SiON with specific thickness and different extinction coefficient (k) as the ARC, comprising: (a) Depositing pad oxide/silicon nitride on a substrate as a hard mask for etching; (b) Depositing a layer of high extinction coefficient SiON on said silicon nitride, then depositing a layer of low extinction coefficient SiON as the ARC; (c) Exposing by using a STI mask and developing to form an etching mask of said STI; (d) Etching said SiON, silicon nitride, pad oxide and said substrate to form a shallow trench; (e) Growing an oxide layer on the side-wall and the bottom of said shallow trench to remove damage and decrease leakage; (f) Depositing an oxide layer on said shallow trench and said silicon nitride to fill said shallow trench; (g) planarizing by CMP.

Abstract translation: 本发明公开了浅沟槽隔离（STI）的制造方法。 通过利用沉积具有特定厚度和不同消光系数（k）的两层SiON作为ARC，包括：（a）在衬底上沉积衬垫氧化物/氮化硅作为用于蚀刻的硬掩模; （b）在所述氮化硅上沉积一层高消光系数SiON，然后沉积一层低消光系数SiON作为ARC; （c）通过使用STI掩模曝光并显影以形成所述STI的蚀刻掩模; （d）蚀刻所述SiON，氮化硅，衬垫氧化物和所述衬底以形成浅沟槽; （e）在浅沟槽的侧壁和底部生长氧化层，以消除损坏并减少泄漏; （f）在所述浅沟槽和所述氮化硅上沉积氧化物层以填充所述浅沟槽; （g）通过CMP平面化。

公开(公告)号：US06845444B2

公开(公告)日：2005-01-18

申请号：US09934574

申请日：2001-08-23

Applicant: Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

Inventor： Jen-Pin Su ,  Chun-Chieh Wu ,  Chao-Yu Chen

IPC: G06F3/00 ,  G06F9/24 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4004 ,  G06F13/423 ,  G06F2213/0024

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state. Subsequently, the configuration value fetched from the non-volatile memory is asserted to the at least one configurable device to configure the configurable device, and then the processor reset signal is deasserted, and the at least one configurable device is thereby completely configured.

Abstract translation: 提供了一种减少具有至少一个可配置设备的计算机系统中的捆扎设备的方法，其包括以下步骤。 首先提供存储在非易失性存储器中的配置值。 在计算机系统的上电和复位期间，高速外设总线的处理器复位信号和总线复位信号都被断言，其中高速外设总线被包括在计算机系统中。 当高速外设总线的工作时钟达到其工作电压和频率时，从非易失性存储器中取出配置值。 取出步骤被重复，直到获取的配置值的最高有效位（MSB）从第一状态改变到第二状态。 随后，从非易失性存储器取出的配置值被断言给至少一个可配置设备以配置可配置设备，然后解除处理器复位信号，并且由此完全配置至少一个可配置设备。

公开(公告)号：US06845414B2

公开(公告)日：2005-01-18

申请号：US10099236

申请日：2002-03-15

Applicant: Fu-Chou Hsu ,  Kuo-Wei Yeh

Inventor： Fu-Chou Hsu ,  Kuo-Wei Yeh

IPC: G06F7/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/14 ,  G11C7/00 ,  G11C7/10 ,  G11C11/00 ,  H03M7/16

CPC classification number: G06F5/14 ,  G06F2205/102 ,  G06F2213/0038 ,  H03M7/16

Abstract: An apparatus and method for controlling an asynchronous First-In-First-Out (FIFO) memory. The asynchronous FIFO has separate, free running read and write clocks. A number of n-bit circular Gray code counters are used to handshake the operation between read and write parts of the FIFO, wherein n is any integer more than one. Additional binary counters are used to accumulate the read and write overflows for the circular Gray code counters. When any circular Gray code counter is overflow, the read or write count is transferred to the respective binary counter for recording the FIFO accesses.

Abstract translation: 一种用于控制异步先入先出（FIFO）存储器的装置和方法。 异步FIFO具有独立的，自由运行的读和写时钟。 使用多个n位圆形格雷码计数器来握握FIFO的读取和写入部分之间的操作，其中n是多于一个的整数。 附加的二进制计数器用于累积循环格雷码计数器的读写溢出。 当任何圆形格雷码计数器溢出时，读取或写入计数被传送到相应的二进制计数器，用于记录FIFO访问。

公开(公告)号：US06838756B2

公开(公告)日：2005-01-04

申请号：US10227266

申请日：2002-08-26

Applicant: Wei-Feng Lin ,  Chung-Ju Wu ,  Chen-Wen Tsai

Inventor： Wei-Feng Lin ,  Chung-Ju Wu ,  Chen-Wen Tsai

IPC: H01L23/13 ,  H01L23/495

CPC classification number: H01L23/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip-packaging substrate. The substrate is capable of reducing damage during packaging, shrinking its connecting portions so that the length of any of the gap slots between the packaging portion and the frame portion of the substrate is increased. Furthermore, a dummy layer is provided to one surface of the frame portion to flush the surface on the frame portion with that of the packaging portion as much as possible.

Abstract translation: 芯片封装基板。 该基板能够减少封装期间的损坏，使其连接部分收缩，使得封装部分和基板的框架部分之间的任何间隙的长度增加。 此外，在框架部分的一个表面上设置虚拟层，以尽可能多地将框架部分的表面与包装部分的表面齐平。

公开(公告)号：US20040201597A1

公开(公告)日：2004-10-14

申请号：US10409131

申请日：2003-04-09

Applicant: SILICON INTEGRATED SYSTEMS CORP.

Inventor： Wen-Kuo Lin

IPC: G09G005/00

CPC classification number: G06T5/002 ,  G06T5/003 ,  G06T5/009 ,  G06T5/20

Abstract: A method for adjusting sharpness and brightness of a digital image. In this method, an image function is first inputted into a processor. The image function comprises a plurality of control parameters. Next, the control parameter values of the control parameters are set, and then each of the pixels is sequentially leaded into the image function according to the control parameter value so as to perform the corresponding operation for adjusting the sharpness and brightness of the image. Finally, the adjusted image is outputted. Therefore, the two processes in the prior art, one for adjusting the brightness, the other for the sharpness, are merged into one process so that the design of the hardware circuit is simplified and the required memory space is reduced.

Abstract translation: 一种用于调整数字图像的清晰度和亮度的方法。 在该方法中，首先将图像功能输入到处理器中。 图像功能包括多个控制参数。 接下来，设置控制参数的控制参数值，然后根据控制参数值将每个像素依次引导到图像功能中，以便执行用于调整图像的清晰度和亮度的相应操作。 最后，输出调整后的图像。 因此，现有技术中用于调整亮度的两个过程，另一个用于锐度，被合并成一个过程，从而简化了硬件电路的设计并减少了所需的存储器空间。

公开(公告)号：US20040090289A1

公开(公告)日：2004-05-13

申请号：US10291530

申请日：2002-11-12

Applicant: Silicon Integrated Systems Corp.

Inventor： Tsun-hsu Chang

IPC: H01P007/00

CPC classification number: H01P7/082 ,  H05K1/0216 ,  H05K2201/09309 ,  H05K2203/162 ,  H05K2203/171

Abstract: An approach to enhance the noise immunity of high-speed digital signals by means of a resonance-free environment is developed. Resonance detuning is achieved by appropriately reshaping the layout of the power/ground planes. Resonant properties of the power distribution system, including resonant frequencies and field distribution profiles, were characterized with frequency-domain simulations. Analysis of the resonant field profiles reveals that the electric field distribution of the dominant mode normally concentrates in the vicinity of the plane edge. Therefore, resonance can be effectively tuned out of the operating frequency range through boundary configuring. In addition, it is shown that variation of the quality factor with the external probe position provides a means to monitor and construct the resonant field distribution. Physical mechanism responsible for this unique property is clarified from the perspective of probe coupling. A Y-shaped layout is reshaped to effectively realize a resonance-free operating environment.

Abstract translation: 开发了一种通过无共振环境提高高速数字信号的抗噪声性的方法。 谐振失谐是通过适当重新形成电源/接地层的布局来实现的。 配电系统的谐振特性，包括谐振频率和电场分布曲线，通过频域模拟进行了表征。 谐振场分布的分析表明，主模的电场分布通常集中在平面边缘附近。 因此，可以通过边界配置有效地将谐振调谐到工作频率范围之外。 另外，显示了质量因子与外部探针位置的变化提供了监测和构建谐振场分布的手段。 从探头耦合的角度阐明了负责这种独特性质的物理机制。 重新形成Y形布局，以有效实现无共振的操作环境。

公开(公告)号：US20040010532A1

公开(公告)日：2004-01-15

申请号：US10191214

申请日：2002-07-09

Applicant: Silicon Integrated Systems Corp.

Inventor： Chung-Yen Lu

IPC: G06F007/38

CPC classification number: G06F7/483

Abstract: An apparatus for computing a logarithm to a base p of a floating-point number X. The floating-point number X is represented in the format of (null1)Sxnull2ExnullMx, where Mxnull(1nullfx)null(1nullAxnull2nullK)null(Bxnull2nullN), where Sx is a sign, Ex is an exponent, Mx is a mantissa, 1nullMx

Abstract translation: 用于计算浮点数X的基数p的对数的装置。浮点数X以（-1） .2 .Mx的格式表示，其中Mx =（1 + fx）=（1 + Ax.2 <-K>）+（Bx.2 <-N>），其中Sx是符号，Ex是指数，Mx是尾数，1 <= Mx <2，Fx 是N位分数，Ax是fx的最高K位的值，Bx是fx，0 <= K