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    Rivet design for enhanced copper thick-film I/O pad adhesion
    141.
    发明授权
    Rivet design for enhanced copper thick-film I/O pad adhesion 失效
    铆钉设计用于增强铜厚膜I / O垫附着力

    公开(公告)号：US5389743A

    公开(公告)日：1995-02-14

    申请号：US993544

    申请日：1992-12-21

    Applicant: Charles E. Simila ,  Mradul Mehrotra

    Inventor： Charles E. Simila ,  Mradul Mehrotra

    IPC: H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K1/14 ,  H05K3/28 ,  H05K3/40 ,  H05K1/02

    CPC classification number: H05K1/113 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/017 ,  H05K2201/0979 ,  H05K3/28 ,  H05K3/4053

    Abstract: A ceramic circuit card (10) for a missile utilizing a "rivet" design and a method for making the same wherein thick-film copper I/O pads (15) are fabricated on a first dielectric layer (13) and on the upper surface of conducting material (20) in vias (14) formed in the dielectric layer (13). A first conductor layer (11) is printed directly on an alumina ceramic layer (12). The dielectric layer (13) is then printed on the first conductor layer (11) and on the alumina ceramic layer (12). During operation, each I/O pad (15) has attached to it a flex harness (21) for connecting the card (10) to a printed wiring board (22) on which the card (10) is mounted. The ceramic circuit card (10) is further comprised of additional dielectric and conductor layers in an alternating stacked arrangement. The top conductor layer is used to connect the circuit card to other electrical components.

    Abstract translation: 一种利用“铆钉”设计的导弹的陶瓷电路卡（10）及其制造方法，其中厚膜铜I / O焊盘（15）制造在第一电介质层（13）上并且在上表面 在介质层（13）中形成的通路（14）中的导电材料（20）。 第一导体层（11）直接印在氧化铝陶瓷层（12）上。 然后将介电层（13）印刷在第一导体层（11）和氧化铝陶瓷层（12）上。 在操作期间，每个I / O焊盘（15）已经附接有用于将卡（10）连接到其上安装有卡（10）的印刷线路板（22）的柔性线束（21）。 陶瓷电路卡（10）还包括交替堆叠布置的附加电介质层和导体层。 顶部导体层用于将电路卡连接到其他电气部件。

    Refractory covercoat for semicondutor devices and methods of making and using the same
    142.
    发明授权
    Refractory covercoat for semicondutor devices and methods of making and using the same 失效
    半导体器件用耐火保护层及其制作及使用方法

    公开(公告)号：US5190793A

    公开(公告)日：1993-03-02

    申请号：US818946

    申请日：1992-01-10

    Applicant: Carl W. Berlin ,  John K. Isenberg

    Inventor： Carl W. Berlin ,  John K. Isenberg

    IPC: H01L21/48 ,  H05K1/09 ,  H05K3/28

    CPC classification number: H05K3/285 ,  H01L21/481 ,  H01L21/4867 ,  H05K1/092 ,  H05K2201/017

    Abstract: Disclosed is a refractory covercoat composition useful in making two-sided circuitries. The refractory composition contains glass frit, and an inorganic binder including at least one selected from the group consisting of ZrO.sub.2, Al.sub.2 O.sub.3, SiO.sub.2, BaO, CaO, MgO and La.sub.2 O.sub.3. The refractory covercoat has an elevated softening point so that the covercoat protects a printed conductor circuit from damage due to contact with a firing furnace conveyor belt.

    Abstract translation: 公开了用于制造双面电路的耐火涂层组合物。 耐火材料组合物含有玻璃料，以及包含选自ZrO 2，Al 2 O 3，SiO 2，BaO，CaO，MgO和La 2 O 3中的至少一种的无机粘合剂。 耐火覆盖层具有升高的软化点，使得覆盖层保护印刷导体电路免受与烧制炉输送带接触的损坏。

    Glasses and overglaze inks made therefrom
    143.
    发明授权
    Glasses and overglaze inks made therefrom 失效
    由此制成的眼镜和釉面油墨

    公开(公告)号：US5124282A

    公开(公告)日：1992-06-23

    申请号：US616498

    申请日：1990-11-21

    Applicant: Ashok N. Prabhu

    Inventor： Ashok N. Prabhu

    IPC: C03C8/04 ,  H01B3/08 ,  H05K1/03 ,  H05K3/28

    CPC classification number: C03C8/04 ,  H01B3/087 ,  H05K1/0306 ,  H05K3/285 ,  H05K2201/017

    Abstract: A novel devitrifying glass comprising, in weight percent, from 5-15% of zinc oxide, from 10-18% of magnesium oxide; from 15-20% of calcium oxide; from 6-14% of barium oxide; from 15-20% of aluminum oxide and from 30-40% of silicon dioxide. The glasses are thermally matched to alumina substrates. The glasses form overglaze thick film inks when admixed with an organic vehicle that are useful as protective coatings for alumina substrates and multilayer printed circuits.

    Abstract translation: 一种新型的失透玻璃，其以重量百分比计含有5-15％的氧化锌，10-18％的氧化镁; 15-20％的氧化钙; 6-14％的氧化钡; 15-20％的氧化铝和30-40％的二氧化硅。 玻璃与氧化铝基底热匹配。 当与用作氧化铝基底和多层印刷电路的保护涂层的有机载体混合时，眼镜形成釉面厚膜油墨。

    Thick-film circuit arrangement having a ceramic substrate plate
    144.
    发明授权
    Thick-film circuit arrangement having a ceramic substrate plate 失效
    具有陶瓷基板的厚膜电路装置

    公开(公告)号：US4839775A

    公开(公告)日：1989-06-13

    申请号：US208853

    申请日：1988-06-14

    Applicant: Wolfgang E. Schnitker ,  Michael P. J. Nover ,  Kay Appel

    Inventor： Wolfgang E. Schnitker ,  Michael P. J. Nover ,  Kay Appel

    IPC: H05K3/46 ,  H01L25/16 ,  H01L27/01 ,  H05K1/09 ,  H05K1/16 ,  H05K3/28

    CPC classification number: H01L25/16 ,  H01L27/013 ,  H05K3/28 ,  H01L27/02 ,  H01L2924/0002 ,  H05K1/0275 ,  H05K1/092 ,  H05K1/16 ,  H05K2201/017 ,  H05K2201/0195 ,  H05K2201/09881 ,  H05K2203/0577 ,  Y10S428/901

    Abstract: The invention relates to a thick-film circuit arrangement having an electronic circuit which is constructed on a surface (17) of a ceramic substrate plate (3) and which consists of conductor paths (5), resistors, capacitors and components, in particular integrated switching circuits without a housing, formed according to thick-film technique. This structure has between the electrically conductive structures (5) a sintered, nonconductive paste substantially filling the intermediate spaces between them and both the structures and the interposed pastes are covered by a sintered insulating paste. For concealing the thick-film circuit arrangement from unauthorized access, the following covering construction is carried out:1. the paste in the intermediate spaces fills the same between the electrically active thick-film conductor structures in such a manner that the tops of the electrically active structures and the insulating filling layer (7) formed from an insulating paste and filling the intermediate spaces between them are situated substantially in one plane, and2. the insulating paste is provided over the combined conductor/filling layer (11) in a covering and smoothing manner to form at least one insulating first thick-film anti-access layer (13) which, by additional observation-impeding inclusions (dyes, particles) impedes an optical recognition of the underlying structures, especially when the first thick-film anti-access layer or layers is or are not succeeded by further anti-access layers.

    Abstract translation: 本发明涉及一种具有电子电路的厚膜电路装置，该电子电路构造在陶瓷基板（3）的表面（17）上并由导体路径（5），电阻器，电容器和部件组成，特别是集成 没有外壳的开关电路，根据厚膜技术形成。 这种结构在导电结构（5）之间具有基本上填充它们之间的中间空间的烧结的非导电糊，两个结构和插入的糊状物被烧结绝缘膏覆盖。 为了隐藏厚膜电路装置以防止未经授权的访问，执行以下覆盖结构：1.中间空间中的糊料以这样的方式填充电活性厚膜导体结构之间，使得电气 主要结构和由绝缘膏形成并填充它们之间的中间空间的绝缘填充层（7）基本上位于一个平面中，并且2.绝缘膏被提供在组合的导体/填充层（11）上，覆盖 以及平滑方式形成至少一个绝缘的第一厚膜反接触层（13），其通过附加的观察阻碍夹杂物（染料，颗粒）阻止下面的结构的光学识别，特别是当第一厚膜反层 - 接入层或层不再被其他反接入层所取代。

    Method for making porous bottom-layer dielectric composite structure
    145.
    发明授权
    Method for making porous bottom-layer dielectric composite structure 失效
    多孔底层介电复合结构的制备方法

    公开(公告)号：US4724021A

    公开(公告)日：1988-02-09

    申请号：US888567

    申请日：1986-07-23

    Applicant: Paul J. Martin ,  Thomas E. Dueber

    Inventor： Paul J. Martin ,  Thomas E. Dueber

    IPC: C04B35/00 ,  C04B38/00 ,  C04B41/52 ,  H01B3/08 ,  H01L21/48 ,  H05K1/00 ,  H05K1/03 ,  H05K3/46 ,  B32B18/00 ,  B32B31/26

    CPC classification number: H05K3/28 ,  C04B41/52 ,  H01L21/4807 ,  H05K3/4667 ,  C04B2111/00844 ,  H05K1/0306 ,  H05K2201/0116 ,  H05K2201/017 ,  H05K2201/0195

    Abstract: A method for inhibiting the formation of blisters during the firing of intermediate layers of fired multilayer electronic components comprising the sequential steps of:(1) applying to a substrate a first and second layer of finely divided particles of dielectric solids and glass dispersed in organic medium; and(2) firing the layers to effect volatilization of the organic medium therefrom, liquid phase sintering of the glass components and densification of both layers, the softening point of the glass, the particle size of the glass and the ratio of glass to dielectric solids in both layers being adjusted in such manner that when the layers are fired, the first layer is porous and the second layer is nonporous.

    Abstract translation: 一种用于在燃烧的多层电子部件的中间层的烧制过程中抑制起泡形成的方法，包括以下顺序步骤：（1）向介质施加第一和第二层细小的电介质固体颗粒和分散在有机介质中的玻璃 ; 和（2）焙烧层以实现有机介质的挥发，玻璃组分的液相烧结和两层致密化，玻璃的软化点，玻璃的粒径和玻璃与介电固体的比例 在这两个层中的调节方式是当这些层被烧制时，第一层是多孔的，而第二层是无孔的。

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