公开(公告)号：US20080318478A1

公开(公告)日：2008-12-25

申请号：US12114600

申请日：2008-05-02

Applicant: Stephen T. Nelson ,  Donald A. Ice ,  Darin James Douma

Inventor： Stephen T. Nelson ,  Donald A. Ice ,  Darin James Douma

IPC: H01R13/66 ,  H01R24/00

CPC classification number: H01R12/52 ,  H05K1/0219 ,  H05K1/117 ,  H05K1/141 ,  H05K1/142 ,  H05K3/185 ,  H05K2201/09118 ,  H05K2201/09154 ,  H05K2201/09236 ,  H05K2203/107 ,  Y10S439/931

Abstract: An edge connector suitable for attachment with a printed circuit board. The edge connector comprises a body composed of a plastic resin, the body defining a first end that is configured to operably attach to a portion of a printed circuit board and a second end configured to operably connect to a slot in a host device and a plurality of conductive traces and contact pads defined on a portion of a surface of the body, the traces being configured to electrically connect with corresponding traces defined on the printed circuit board.

Abstract translation: 适用于与印刷电路板连接的边缘连接器。 边缘连接器包括由塑料树脂构成的主体，主体限定第一端，其构造成可操作地附接到印刷电路板的一部分，并且第二端被配置为可操作地连接到主机设备中的槽，并且多个 导电迹线和限定在主体表面的一部分上的接触焊盘，迹线被配置为与印刷电路板上限定的相应迹线电连接。

公开(公告)号：US20080235939A1

公开(公告)日：2008-10-02

申请号：US12033851

申请日：2008-02-19

Applicant: Siew S. Hiew ,  Charles C. Lee ,  Paul Hsueh ,  Abraham C. Ma ,  Ming-Shiang Shen

Inventor： Siew S. Hiew ,  Charles C. Lee ,  Paul Hsueh ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC: H05K3/20 ,  G11C11/34

CPC classification number: H05K3/284 ,  H01L21/561 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1815 ,  H05K1/117 ,  H05K3/0032 ,  H05K3/0052 ,  H05K2201/09154 ,  H05K2201/10159 ,  H05K2203/0228 ,  H05K2203/0746 ,  H05K2203/1316 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49171 ,  Y10T29/49789 ,  Y10T29/49798 ,  H01L2224/85 ,  H01L2924/00

Abstract: A method for fabricating MicroSD devices includes forming a PCB panel having multiple PCB regions arranged in parallel rows. Passive components are attached by conventional surface mount technology (SMT) techniques. IC chips, including a MicroSD controller chip and a flash memory chip, are attached to the PCB by wire bonding or other chip-on-board (COB) technique. A molded layer is then formed over the IC chips and passive components using a mold that prevents formation of plastic on the upper surface of each PCB. The panel is then singulated using one of a laser cutting method, an abrasive water jet cutting method, and a mechanical grinding method such that the resulting PCB substrate and plastic housing have the width, height and length specified by MicroSD specifications. A front edge chamfer process is then performed.

Abstract translation: 一种用于制造MicroSD器件的方法包括形成具有平行排布置的多个PCB区域的PCB面板。 无源元件通过常规表面贴装技术（SMT）技术连接。 包括MicroSD控制器芯片和闪存芯片在内的IC芯片通过引线接合或其他芯片上的（COB）芯片技术连接到PCB。 然后使用防止在每个PCB的上表面上形成塑料的模具在IC芯片和无源部件上形成模制层。 然后使用激光切割方法，磨料水射流切割方法和机械研磨方法之一将面板切片，使得所得PCB基板和塑料外壳具有由MicroSD规格规定的宽度，高度和长度。 然后执行前沿倒角处理。

公开(公告)号：US07416132B2

公开(公告)日：2008-08-26

申请号：US10851466

申请日：2004-05-20

Applicant: Hem P. Takiar ,  Robert Miller

Inventor： Hem P. Takiar ,  Robert Miller

IPC: G06K19/06

CPC classification number: G06K19/07732 ,  G06K13/0825 ,  G06K19/077 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01004 ,  H01L2924/1815 ,  H01L2924/19041 ,  H05K1/02 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/09045 ,  H05K2201/09154 ,  H05K2203/0271 ,  Y10T29/4913 ,  H01L2924/00014

Abstract: The present invention, roughly described, pertains to a small memory card that includes features which allow the memory card to be more easily handled by a user. In various embodiments, the memory card can include a chamfer and/or a raised portion that allows the memory card to be more easily grabbed by a human hand (or mechanical device) and also provides additional room to store passive devices such as capacitors and/or resistors. Because different electronic devices use different types of memory cards, an adaptor is provided that allows the memory cards disclosed herein to be used in ports or connectors on electronic devices that are meant for other types of memory cards.

Abstract translation: 大致描述的本发明涉及一种小型存储卡，其包括允许存储卡更容易由用户处理的特征。 在各种实施例中，存储卡可以包括倒角和/或凸起部分，其允许存储卡被人的手（或机械装置）更容易地抓住，并且还提供额外的空间以存储诸如电容器和/ 或电阻。 因为不同的电子设备使用不同类型的存储卡，所以提供了一种适配器，其允许本文所公开的存储卡被用在用于其他类型的存储卡的电子设备上的端口或连接器中。

公开(公告)号：US20080187722A1

公开(公告)日：2008-08-07

申请号：US11672258

申请日：2007-02-07

Applicant: Jaime I. Waldman

Inventor： Jaime I. Waldman

IPC: B32B33/00 ,  B23K31/02

CPC classification number: H05K3/3442 ,  H01L23/13 ,  H01L23/49805 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2924/0002 ,  H05K2201/09154 ,  H05K2201/10727 ,  Y02P70/613 ,  Y10T428/24777 ,  H01L2924/00

Abstract: A method for surface mounting a leadless chip carrier to a circuit board, the method includes the steps of providing the leadless chip carrier with chamfered edges along one or more sides and with package metallic connection portions disposed along one or more chamfered edges; providing the circuit board with a plurality of circuit board metallic connection portions; placing a layer of solder onto the circuit board metallic connection; placing the leadless chip carrier on the circuit board with the package metallic connections, layer of solder and the circuit board metallic connections aligned; and heating the leadless chip carrier and the circuit board so the layer of solder forms a solder joint with the package metallic connection portions and the circuit board metallic connections.

Abstract translation: 一种用于将无引线芯片载体表面安装到电路板的方法，所述方法包括以下步骤：沿着一个或多个侧面提供无引线芯片载体的倒角边缘，以及沿一个或多个倒角边缘设置的封装金属连接部分; 为电路板提供多个电路板金属连接部分; 将一层焊料放置在电路板金属连接上; 将无引线芯片载体放置在具有封装金属连接的电路板上，焊料层和电路板金属连接对齐; 并加热无铅芯片载体和电路板，使得焊料层与封装金属连接部分和电路板金属连接形成焊接点。

公开(公告)号：US07388279B2

公开(公告)日：2008-06-17

申请号：US10987187

申请日：2004-11-12

Applicant: Joseph C. Fjelstad ,  Kevin P. Grundy ,  Para K. Segaram ,  Gary Yasumura

Inventor： Joseph C. Fjelstad ,  Kevin P. Grundy ,  Para K. Segaram ,  Gary Yasumura

IPC: H01L23/58

CPC classification number: H05K1/0243 ,  G01R31/2822 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/1903 ,  H01L2924/19039 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01P3/08 ,  H01P5/028 ,  H05K1/024 ,  H05K2201/0191 ,  H05K2201/09154 ,  H05K2201/09727 ,  Y10S438/981 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.

Abstract translation: 公开了锥形电介质和导体结构，其提供受控的阻抗互连，同时信号导体线从更细的间距转换到较粗的间距，从而消除通常与电路接触间距的变化相关的电中断。 还公开了用于构造装置和应用的方法。

公开(公告)号：US20070270040A1

公开(公告)日：2007-11-22

申请号：US11381877

申请日：2006-05-05

Applicant: Sang Jang ,  Chul Park ,  Jong Choi ,  Jae Kim ,  Choon Lee

Inventor： Sang Jang ,  Chul Park ,  Jong Choi ,  Jae Kim ,  Choon Lee

IPC: H01R24/00

CPC classification number: G06K19/077 ,  H05K1/117 ,  H05K2201/09154 ,  H05K2201/2018

Abstract: A memory card including a printed circuit board having an electronic circuit device mounted thereto and at least one I/O pad disposed thereon. The printed circuit board and the electronic circuit device are at least partially encapsulated or covered by an encapsulant material which hardens into a body of the memory card, such body generally defining the outer appearance of the memory card. The I/O pads of the printed circuit board are exposed in the body. The body is formed to include one or more chamfers. Such chamfer(s) are sized and configured to minimize potential damage to the connection terminals or host socket of a device during the process of interfacing the memory card thereto.

Abstract translation: 一种存储卡，包括具有安装在其上的电子电路装置的印刷电路板和设置在其上的至少一个I / O焊盘。 印刷电路板和电子电路装置至少部分地被密封剂材料封装或覆盖，所述密封剂材料硬化到存储卡的主体中，该主体通常限定存储卡的外观。 印刷电路板的I / O焊盘暴露在体内。 该主体形成为包括一个或多个倒角。 这种倒角的尺寸和构造被设计成使得在将存储卡与其接口的过程中对设备的连接端子或主机插座的潜在损坏最小化。

公开(公告)号：US07113389B2

公开(公告)日：2006-09-26

申请号：US11149304

申请日：2005-06-10

Applicant: Michiru Ishifune ,  Yoji Tozawa ,  Toshiyuki Anbo ,  Hidekazu Sato ,  Shuumi Kumagai

Inventor： Michiru Ishifune ,  Yoji Tozawa ,  Toshiyuki Anbo ,  Hidekazu Sato ,  Shuumi Kumagai

IPC: H01G4/228 ,  H01G2/20

CPC classification number: H01G2/065 ,  H01F17/0013 ,  H01F27/292 ,  H05K3/3442 ,  H05K2201/09154 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/417

Abstract: A multilayer inductor has a rectangular parallelepiped element body and its length in the lengthwise direction (L), length in the direction of height (H), and length in the direction of width (W) are L≦0.6 mm, H≦0.3 mm, and W≦0.3 mm, respectively. Terminal electrodes are provided so as to cover the vertices of the element body and come round to the side face from the end faces on both sides. The radius of curvature R of the vertex of the terminal electrode is set to a value being 10% or more and 20% or less of H or W.

Abstract translation: 多层电感器具有长方体元件体，其长度方向（L）的长度，高度方向的长度（H）和宽度方向的长度（W）的长度L <= 0.6mm，H <= 0.3mm，W <= 0.3mm。 端子电极被设置成覆盖元件主体的顶点并从两侧的端面到达侧面。 端子电极的顶点的曲率半径R被设定为H或W的10％以上且20％以下的值。

公开(公告)号：US20060084285A1

公开(公告)日：2006-04-20

申请号：US11292082

申请日：2005-12-02

Applicant: Thomas Muench

Inventor： Thomas Muench

IPC: H01R12/00

CPC classification number: H01L24/05 ,  H01L23/057 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85399 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/113 ,  H05K1/117 ,  H05K1/185 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09154 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2203/049 ,  H05K2203/1461 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: A circuit carrier includes a substrate with two oppositely arranged areas. The terminal contacts of a flat connector strip are arranged in the edge regions of the areas. A through contact is arranged under at least one of the terminal contacts with concealed electrical connection to the rear side of the terminal contact and the top side of the terminal contact exhibits an undisturbed morphology and planar surface.

Abstract translation: 电路载体包括具有两个相对布置区域的衬底。 扁平连接器条的端子触点布置在区域的边缘区域中。 在至少一个端子触点之下布置有一个贯通触点，其中，与端子触点的后侧具有隐蔽的电连接，并且端子触点的顶侧呈现出不受干扰的形态和平坦表面。

公开(公告)号：US20060007640A1

公开(公告)日：2006-01-12

申请号：US11149304

申请日：2005-06-10

Applicant: Michiru Ishifune ,  Yoji Tozawa ,  Toshiyuki Anbo ,  Hidekazu Sato ,  Shuumi Kumagai

Inventor： Michiru Ishifune ,  Yoji Tozawa ,  Toshiyuki Anbo ,  Hidekazu Sato ,  Shuumi Kumagai

IPC: H01G9/00

CPC classification number: H01G2/065 ,  H01F17/0013 ,  H01F27/292 ,  H05K3/3442 ,  H05K2201/09154 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/417

Abstract: A multilayer inductor has a rectangular parallelepiped element body and its length in the lengthwise direction (L), length in the direction of height (H), and length in the direction of width (W) are L≦0.6 mm, H≦0.3 mm, and W≦0.3 mm, respectively Terminal electrodes are provided so as to cover the vertices of the element body and come round to the side face from the end faces on both sides. The radius of curvature R of the vertex of the terminal electrode is set to a value being 10% or more and 20% or less of H or W.

Abstract translation: 多层电感器具有长方体元件体，其长度方向（L）的长度，高度方向的长度（H）和宽度方向的长度（W）的长度L <= 0.6mm，H <= 0.3mm，W <= 0.3mm。端子电极被设置成覆盖元件主体的顶点并从两侧的端面到达侧面。 端子电极的顶点的曲率半径R被设定为H或W的10％以上且20％以下的值。

公开(公告)号：US06979906B2

公开(公告)日：2005-12-27

申请号：US10698725

申请日：2003-10-30

Applicant: Hubert Allen Vander Plas ,  Frank Berauer

Inventor： Hubert Allen Vander Plas ,  Frank Berauer

IPC: H01L21/60 ,  H01L23/485 ,  H01L29/06 ,  H05K3/34 ,  H05K3/40 ,  H01L29/40

CPC classification number: H05K3/3484 ,  H01L24/11 ,  H01L24/13 ,  H01L29/0657 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10157 ,  H05K3/3452 ,  H05K3/403 ,  H05K2201/09154 ,  H05K2201/099 ,  H05K2203/0568 ,  H05K2203/1394 ,  H01L2224/0401

Abstract: A method for depositing a solder layer or solder bump on a sloped surface. The method includes etching a sloped surface on a planar semiconductor substrate, depositing a solder-wettable layer on the sloped surface, masking the wettabler layer with a coating layer to control the position of the solder deposition, and using an organic film to prevent the solder from being deposited at regions not above either the wettable layer or the coating layer. Also, a semiconductor device structure on which a solder layer or solder bump is formed exclusively on a sloped surface.

Abstract translation: 一种用于在倾斜表面上沉积焊料层或焊料凸块的方法。 该方法包括蚀刻平面半导体衬底上的倾斜表面，在倾斜表面上沉积焊料可润湿层，用涂层掩蔽湿润层以控制焊料沉积的位置，并使用有机膜防止焊料 不会沉积在可湿性层或涂层之上的区域。 此外，其中仅在倾斜表面上形成焊料层或焊料凸块的半导体器件结构。