公开(公告)号：US06641898B2

公开(公告)日：2003-11-04

申请号：US10024470

申请日：2001-12-21

Applicant: Yoshitaro Yazaki ,  Yoshihiko Shiraishi ,  Koji Kondo ,  Toshikazu Harada ,  Tomohiro Yokochi

Inventor： Yoshitaro Yazaki ,  Yoshihiko Shiraishi ,  Koji Kondo ,  Toshikazu Harada ,  Tomohiro Yokochi

IPC: B32B300

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T428/24917

Abstract: A heated and pressed printed wiring board is made by filling via holes formed in layers of insulating film of the wiring board with an interlayer conducting material. The insulating film is stacked with conductor patterns, and each conductor pattern closes a via hole. The interlayer conducting material forms a solid conducting material in the via holes after a heating a pressing procedure. The solid conducting material includes two types of conducting materials. The first type of conducting material includes a metal, and the second type of conductive material includes an alloy formed by the metal and conductor metal of the conductor patterns. The conductor patterns are electrically connected reliably without relying on mere mechanical contact.

公开(公告)号：US06628128B1

公开(公告)日：2003-09-30

申请号：US09651860

申请日：2000-08-30

Applicant: Warren M. Farnworth ,  Derek J. Gochnour ,  David R. Hembree

Inventor： Warren M. Farnworth ,  Derek J. Gochnour ,  David R. Hembree

IPC: G01R3102

CPC classification number: H05K1/112 ,  G01R1/0483 ,  H05K3/325 ,  H05K2201/09472 ,  H05K2201/09827 ,  H05K2201/10734

Abstract: A BGA test socket for use in standard testing and burn-in testing of BGA dies and method for testing such dies is disclosed wherein a die contact insert made of silicon or ceramic using standard IC fabrication technology is used. Through using such an insert, even small scale (pitch) BGA dies can be reliably tested including chip scale packaged (“CSP”) BGA dies. Furthermore, using such an insert allows a conventional socket to be adapted for use with a wide variety of both BGA dies and other varieties. A method for using the device is disclosed which overcomes current static electricity problems experienced in testing CSP BGA dies through closing the test socket before removing the die deposit probe.

公开(公告)号：US06591496B2

公开(公告)日：2003-07-15

申请号：US09941058

申请日：2001-08-28

Applicant: David C. Koskenmaki ,  Michael N. Miller ,  Naiyong Jing

Inventor： David C. Koskenmaki ,  Michael N. Miller ,  Naiyong Jing

IPC: H05K310

CPC classification number: H05B3/86 ,  G02F1/13439 ,  G02F1/155 ,  H05B3/286 ,  H05B2203/017 ,  H05K3/102 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0133 ,  H05K2201/09036 ,  H05K2201/091 ,  H05K2201/09827 ,  H05K2203/0278 ,  H05K2203/1105 ,  Y10S428/901 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A method for making a fine electrically conductive grid embedded in a polymer substrate. The method includes the steps of providing a polymer substrate, forming a pattern of grooves in the substrate, filling the grooves with electrically conductive powder, and then applying heat and/or pressure to the substrate. The application of heat and/or pressure to the substrate causes the grooves to collapse inward against the conductive powder. Collapsing the grooves compacts the conductive powder within the groove, thereby establishing a continuously conductive grid line or circuit. The narrow grid lines that result allow more light to transmit through the substrate. The method allows grid lines to be made with higher aspect ratios (ratio of line depth to line width) than is possible by previous methods.

Abstract translation: 一种制造嵌入聚合物基板中的精细导电栅格的方法。 该方法包括以下步骤：提供聚合物基材，在基材中形成凹槽图案，用导电粉末填充凹槽，然后向基材施加热和/或压力。 向衬底施加热和/或压力导致沟槽相对于导电粉末向内折叠。 折叠凹槽压缩凹槽内的导电粉末，从而建立连续导电的栅格线或电路。 导致的窄栅格线允许更多的光透过基板。 该方法允许以比以前的方法可能的更高的纵横比（线深度与线宽的比率）制成网格线。

公开(公告)号：US20030121146A1

公开(公告)日：2003-07-03

申请号：US10239731

申请日：2002-11-14

Inventor： Walter Schmidt

IPC: H05K003/02 ,  H05K003/10

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: According to the invention, a microperforation (PMP) process step is combined with the lamination process. To this end, a dielectric layer are and a prefabricated product are placed between a support and a perforation die. The prefabricated product is partially covered by a conducting layer forming structures to be contacted by microvias. Pressure is applied on the perforation die, perforation tips of the perforation die forming microvias for contacting the structures. A surface of the dielectric layer or the prefabricated product is configured or coated to in a manner that the prefabricated product and the dielectric layer stick to each other after the pressure has been applied.

Abstract translation: 根据本发明，将微穿孔（PMP）工艺步骤与层压工艺组合。 为此，介电层和预制产品被放置在支撑件和穿孔模具之间。 预制产品被形成由微孔接触的结构的导电层部分覆盖。 在穿孔模具上施加压力，穿孔模具的穿孔尖端形成用于接触结构的微孔。 在施加压力之后，电介质层或预制产品的表面被构造或涂覆成使得预制产品和电介质层彼此粘合。

公开(公告)号：US06569604B1

公开(公告)日：2003-05-27

申请号：US09345723

申请日：1999-06-30

Applicant: Anilkumar Chinuprasad Bhatt ,  Francis Joseph Downes, Jr. ,  Robert Lee Lewis ,  Voya R. Markovich

Inventor： Anilkumar Chinuprasad Bhatt ,  Francis Joseph Downes, Jr. ,  Robert Lee Lewis ,  Voya R. Markovich

IPC: G03C500

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/4602 ,  H05K2201/09827 ,  H05K2203/1476

Abstract: A blind via structure, and associated laser ablation methods of formation, that includes a blind via within a photoimageable dielectric (PID) layer on a substrate, such that the sidewall of the blind via makes an obtuse angle with the blind end of the blind via. The obtuse-angled sidewall may be formed by executing two processes in sequence. In the first process, photoimaging of the PID layer, with selective exposure to ultraviolet light, results in one or more blind vias having acute-angled sidewalls. The photoimaging cross links the PID material that had been selectively exposed to ultraviolet light such that a subsequent developing step removes PID material not cross linked, or weakly cross linked, to simultaneously form multiple blind vias having different sized openings. In the second process, laser ablation is selectively employed to remove the acute-angled sidewalls from particular blind vias in a way that forms replacement obtuse-angled sidewalls in the laser-ablated blind vias. Alternatively, the first process involving photoimaging may be omitted such that the second step involving laser ablation forms the entire obtuse-angled blind via. The resultant blind via structure includes at least one blind via having an obtuse-angled sidewall, and optionally, at least one blind via having an acute-angled sidewall.

Abstract translation: 盲通孔结构和相关联的激光烧蚀消融方法，其包括在衬底上的可光成像电介质（PID）层内的盲通孔，使得盲通孔的侧壁与盲孔的盲端通过钝角 。 可以通过依次执行两个过程来形成钝角侧壁。 在第一个过程中，通过选择性地暴露在紫外线下的PID层的光成像产生一个或多个具有锐角侧壁的盲孔。 光学成像将选择性暴露于紫外线的PID材料交叉连接，使得随后的显影步骤除去未交联或弱交联的PID材料，以同时形成具有不同尺寸开口的多个盲孔。 在第二过程中，激光烧蚀被选择性地用于在激光烧蚀的盲孔中形成置换钝角侧壁的方式从特定的盲孔中去除锐角侧壁。 或者，可以省略涉及光成像的第一过程，使得涉及激光烧蚀的第二步骤形成整个钝角盲孔。 所得到的盲通孔结构包括至少一个具有钝角侧壁的盲孔，并且可选地，至少一个具有锐角侧壁的盲孔。

公开(公告)号：US20020170876A1

公开(公告)日：2002-11-21

申请号：US10048927

申请日：2002-06-07

Inventor： Eiji Kawamoto ,  Shigeru Yamane ,  Toshiaki Takenaka ,  Toshihiro Nishii

IPC: H01B013/00

CPC classification number: H05K3/4069 ,  H05K2201/0355 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2203/0191 ,  H05K2203/1461 ,  Y10T29/49126

Abstract: A method of manufacturing a PCB comprising the steps of: forming through-holes in a substrate having releasing layers on front and back faces; filling conductive paste in the through-holes; removing the releasing layers and disposing metal foil on both faces of the substrate; and heat pressing them. A diameter of the through-holes is larger than that of corresponding holes formed on the releasing layers. According to the present invention, when the conductive paste is compressed, conductive paste protruding from the surface of the substrate is trapped at the edges of the through-holes. This configuration prevents short circuits with undesirable wiring patterns. So, an enough amount of the conductive paste can protrude from the surface of the substrate. Therefore, after the compression, stable electric connections inside the conductive paste and between the conductive paste and the metal foils are ensured, thus PCBs with superior reliability can be produced.

Abstract translation: 一种制造PCB的方法，包括以下步骤：在前面和背面上形成具有释放层的衬底中的通孔; 在通孔中填充导电膏; 去除释放层并在金属箔的两个面上设置金属箔; 并热压它们。 通孔的直径大于形成在释放层上的相应孔的直径。 根据本发明，当导电膏被压缩时，从基板的表面突出的导电糊被截留在通孔的边缘。 这种配置可以防止出现不良布线图形的短路。 因此，足够量的导电膏可以从基板的表面突出。 因此，在压缩之后，确保导电浆料内部和导电性糊料与金属箔之间的稳定的电连接，从而可以制造出具有高可靠性的PCB。

公开(公告)号：US06448510B1

公开(公告)日：2002-09-10

申请号：US09424179

申请日：2000-06-22

Applicant: Shimon Neftin ,  Uri Mirsky

Inventor： Shimon Neftin ,  Uri Mirsky

IPC: H05K111

CPC classification number: H05K3/445 ,  C25D11/022 ,  C25D11/04 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/02 ,  H05K2201/09827 ,  H05K2203/0315 ,  H05K2203/0323 ,  H05K2203/1142 ,  Y10S428/901 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A substrate for electronic packaging, the substrate having a discrete, generally prismatoid, initially electrically conductive valve metal solid body with one or more spaced apart, original valve metal vias each individually electrically islolated by a porous oxidized body portion therearound. A pin jig fixture for mechanically masking a metal surface, the pin jig fixture having an anodization resistant bed of pins each pin having a leading end surface for intimate juxtaposition against a metal surface to mask portions thereof.

Abstract translation: 一种用于电子封装的衬底，该衬底具有离散的大致棱柱形的最初导电的阀金属固体，其具有一个或多个间隔开的原始阀金属通孔，每个金属孔通过其周围的多孔氧化体部分单独地电绝缘。 一种用于机械地掩蔽金属表面的销夹具夹具，销夹具夹具具有阳极氧化床的销，每个销具有前端表面，用于与金属表面紧密并置以掩盖其部分。

公开(公告)号：US20020113312A1

公开(公告)日：2002-08-22

申请号：US10132960

申请日：2002-04-26

Applicant: 3M Innovative Properties Company

Inventor： William J. Clatanoff ,  Gayle R.T. Schueller ,  Robert J. Schubert ,  Yusuke Saito ,  Hideo Yamazaki ,  Hideaki Yasui

IPC: H01L023/48

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/363 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2201/10681 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A circuit includes a substrate having a dielectric layer with a first surface and a second surface. A conductive layer is formed on the first surface. A beveled via is formed in a dielectric layer of the substrate. The via has a first opening of a first width in the first surface, and a second opening of a second width in the second surface, the second width being greater than the first width. A conductive plug is connected to the conductive layer. The plug is formed in the via and extends from adjacent the first opening toward the second opening, and terminates adjacent the second opening at a plug interface surface. A conductive solder ball is connected to the plug interface surface and extends to protrude from the second surface.

Abstract translation: 电路包括具有第一表面和第二表面的电介质层的衬底。 导电层形成在第一表面上。 在基板的电介质层中形成斜面通孔。 通孔具有第一表面中的第一宽度的第一开口和第二表面中的第二宽度的第二开口，第二宽度大于第一宽度。 导电插头连接到导电层。 插塞形成在通孔中并且从邻近第一开口朝向第二开口延伸并且在插头接口表面处邻近第二开口终止。 导电焊球连接到插头接口表面并延伸以从第二表面突出。

公开(公告)号：US20020079135A1

公开(公告)日：2002-06-27

申请号：US10022222

申请日：2001-12-20

Inventor： Yoshitarou Yazaki ,  Tomohiro Yokochi ,  Koji Kondo ,  Toshikazu Harada ,  Yoshihiko Shiraishi

IPC: H05K001/11 ,  H01R012/04

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: Conductive paste containing tin particles and silver particles is packed in a substantially cylindrical via hole formed in a thermoplastic resin film that interposes between conductor patterns and is hot-pressed from both sides. When the metal particles contained in the conductive paste are sintered to form a unified conductive compound, the volume of the conductive paste shrinks. Synchronously, the resin film around the via-hole protrudes into the via-hole. Therefore, the shape of the side wall on the cross-section of the conductive compound provides an arch shape, and a side wall adjacent to a junction part of the conductive compound, which contacts the conductor pattern, is formed with an inclination. Therefore, it is possible to prevent the stress concentration due to deformation of the board.

Abstract translation: 含有锡颗粒和银颗粒的导电糊料被包装在形成在热塑性树脂膜中的大致圆柱形的通孔中，该热塑性树脂膜介于导体图案之间并且从两侧被热压。 当包含在导电浆料中的金属颗粒被烧结以形成统一的导电化合物时，导电浆料的体积收缩。 同时，通孔周围的树脂膜突出到通孔中。 因此，导电性化合物的横截面上的侧壁的形状形成拱形，并且与导体图案接触的导电性化合物的接合部分相邻的侧壁形成倾斜。 因此，可以防止由于板的变形引起的应力集中。

公开(公告)号：US06373267B1

公开(公告)日：2002-04-16

申请号：US09070339

申请日：1998-04-30

Applicant: Hajime Hiroi

Inventor： Hajime Hiroi

IPC: G01R3102

CPC classification number: H05K1/112 ,  G01R1/0483 ,  H05K3/325 ,  H05K2201/09472 ,  H05K2201/09827 ,  H05K2201/10734

Abstract: A measuring mechanism for a BGA-IC capable of facilitating and assuring the contact between a soldering ball of a BGA-IC and a BGA contact seat even if a foreign matter is sandwiched therebetween, and also capable of saving time involved in recontact therebetween, and of shortening measuring time. The measuring mechanism for a BGA-IC comprising a substrate including a BGA contact seat which is embedded therein and has a conical contact surface, wherein the BGA contact seat is connected to a tester, and the BGA-IC has the soldering ball and wherein the soldering ball contacts the conical contact surface of the BGA contact seat when the BGA-IC is tested.

Abstract translation: 一种用于BGA-IC的测量机构，其能够有助于并确保BGA-IC的焊球与BGA接触座之间的接触，即使异物夹在其间，并且还能够节省涉及其之间的重新调整的时间，以及 缩短测量时间。 一种BGA-IC的测量机构，其特征在于：包括嵌入其中并具有锥形接触表面的BGA接触座的基板，其中所述BGA接触座连接到测试器，并且所述BGA-IC具有所述焊球， 当测试BGA-IC时，焊球与BGA接触座的锥形接触表面接触。