公开(公告)号：US20050139386A1

公开(公告)日：2005-06-30

申请号：US10814803

申请日：2004-04-01

Applicant: Kazuo Tada ,  Koji Kondo ,  Satoshi Takeuchi

Inventor： Kazuo Tada ,  Koji Kondo ,  Satoshi Takeuchi

IPC: H05K3/46 ,  H05K1/16 ,  H05K1/00 ,  H05K3/36

CPC classification number: H05K1/167 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0317 ,  H05K2203/065 ,  Y10T29/49082 ,  Y10T29/49126 ,  Y10T29/49128

Abstract: A multi-layer printed circuit board includes: a resin substrate including a plurality of laminated thermoplastic resin films; a thin film resistor embedded in the resin substrate; and an electrode disposed on the thin film resistor. The thermoplastic resin film includes a conductive pattern made of metallic film. The electrode is covered with the conductive pattern disposed over or under the electrode.

Abstract translation: 多层印刷电路板包括：具有多层叠热塑性树脂膜的树脂基板; 嵌入树脂基板中的薄膜电阻器; 以及设置在薄膜电阻器上的电极。 热塑性树脂膜包括由金属膜制成的导电图案。 电极被设置在电极之上或之下的导电图案覆盖。

公开(公告)号：US06890792B2

公开(公告)日：2005-05-10

申请号：US10645478

申请日：2003-08-22

Applicant: Hiroko Koike ,  Takashi Mochizuki ,  Mitsutoshi Higashi

Inventor： Hiroko Koike ,  Takashi Mochizuki ,  Mitsutoshi Higashi

IPC: H05K1/16 ,  H01G4/33 ,  H01G9/00 ,  H01G9/15 ,  H01L21/20 ,  H01L21/48 ,  H01L21/8242 ,  H01L23/498 ,  H01L51/40 ,  H05K3/30 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01G9/15 ,  H01L21/4857 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0317 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2203/0315 ,  Y10S438/957 ,  Y10T29/417 ,  H01L2924/00

Abstract: A method of formation of a capacitor forming part of an electric circuit when producing a circuit board, consisting of forming a valve metal bottom electrode layer and a valve metal oxide dielectric layer on the same, then integrally forming a solid electrolyte layer comprised of an organic semiconductor and a top electrode layer comprised of metal on the same, this integral formation step consisting of the step of holding one surface of metal foil for the top electrode at a bonding wedge and making the other surface of the metal foil carry a powder of the organic semiconductor by compression bonding and heating and the step of compression bonding the organic semiconductor powder carried by compression bonding at the dielectric layer by a bonding wedge through metal foil, whereby a solid electrolyte layer comprised of an organic semiconductor sandwiched between the metal foil and dielectric layer and closely bonded with the two is formed, a capacitor built into a circuit board, a circuit board including a capacitor, and a method of production of the circuit board.

Abstract translation: 一种电容器形成电容器的形成方法，其特征在于，在制造电路基板时形成电路的一部分，其特征在于，在其上形成阀金属底电极层和阀金属氧化物电介质层，然后一体地形成由有机物构成的固体电解质层 半导体和由其上的金属组成的顶部电极层，该整体形成步骤包括将一个金属箔的表面保持在键合楔形件的顶部电极的一个表面，并使金属箔的另一个表面携带 通过压接和加热的有机半导体，以及通过金属箔通过接合楔将电介质层压接的有机半导体粉末压接的步骤，由此夹在金属箔和电介质之间的有机半导体构成的固体电解质层 形成两层紧密结合的电容器，内置于电路板的电容器，电路 其电路板包括电容器，以及生产电路板的方法。

公开(公告)号：US06889431B2

公开(公告)日：2005-05-10

申请号：US10078448

申请日：2002-02-21

Applicant: Hiroshi Okabe ,  Hirozi Yamada ,  Eriko Takeda ,  Kazunori Yamamoto ,  Hiroyuki Kuriya ,  Masanori Yamaguchi ,  Kazuhisa Otsuka ,  Yoshitaka Hirata ,  Yasushi Shimada

Inventor： Hiroshi Okabe ,  Hirozi Yamada ,  Eriko Takeda ,  Kazunori Yamamoto ,  Hiroyuki Kuriya ,  Masanori Yamaguchi ,  Kazuhisa Otsuka ,  Yoshitaka Hirata ,  Yasushi Shimada

IPC: H01G4/33 ,  H01L21/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/16 ,  H05K3/42 ,  H05K3/46 ,  H05K3/02

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/162 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0338 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a manufacturing method of an electronic circuit device including a multi-layer circuit board incorporated with a thin film capacitor small in size and of high performance capable of attaining higher capacitance value with a thin dielectric film of high dielectric constant and with favorable film quality. A first electrode layer and a thin film dielectric layer are laminated continuously in this order in one identical to laminate each of the layers on a leveled substrate in one identical chamber and then the first electrode layer is fabricated a conductor pattern.

Abstract translation: 本发明提供一种电子电路器件的制造方法，该电子电路器件包括多层电路板，该多层电路板结合有小型和高性能的薄膜电容器，能够用高介电常数的薄电介质膜获得较高的电容值 电影质量。 将第一电极层和薄膜电介质层依次层叠在一个相同的层中，在一个相同的室中的层叠基板上层叠，然后将第一电极层制成导体图案。

公开(公告)号：US20050068748A1

公开(公告)日：2005-03-31

申请号：US10965071

申请日：2004-10-14

Applicant: Tsuyoshi Ogawa

Inventor： Tsuyoshi Ogawa

IPC: H05K3/38 ,  H01L23/12 ,  H01L23/14 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16 ,  H05K1/16 ,  H05K3/06 ,  H05K3/46 ,  H05K7/02

CPC classification number: H01L23/49894 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/498 ,  H01L23/49822 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/16 ,  H05K1/162 ,  H05K1/167 ,  H05K3/062 ,  H05K3/067 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/09509 ,  H05K2203/0315 ,  H05K2203/0361 ,  H05K2203/1453 ,  Y10S438/957 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a thin film circuit board device having passive elements in wiring layers. The thin film circuit board device includes a base board (2) and a circuit part (3) including insulating layers (11) and (16) and pattern wiring (14) and (17) formed on a build-up forming surface (2a). On the first insulating layer (11), a receiving electrode part (21) is formed and the passive elements electrically connected to the receiving electrode part (21) are formed. In the circuit part (3), a substrate titanium film and a substrate film are laminated so as to cover the receiving electrode part (21) and the passive elements respectively. The substrate film and the substrate titanium film in areas in which a metallic film is not formed are etched through the metallic film serving as the first pattern wiring (14) formed on the substrate film as a mask. Thus, a substrate layer (23) and a substrate titanium layer (22) are formed. Consequently, the substrate titanium film serving as the substrate titanium layer (22) prevents the corrosion of the receiving electrode part and the respective passive elements due to etching liquid to form the passive elements with high performance.

Abstract translation: 本发明涉及一种在布线层中具有无源元件的薄膜电路板器件。 薄膜电路板装置包括基板（2）和包括绝缘层（11）和（16）的电路部分（3）和形成在堆积形成表面（2a）上的图案布线（14）和（17） ）。 在第一绝缘层（11）上，形成接收电极部（21），并且形成与接收电极部（21）电连接的无源元件。 在电路部分（3）中，层叠基板钛膜和基板膜以覆盖接收电极部分（21）和无源元件。 通过作为形成在基板膜上的第一图案布线（14）的金属膜作为掩模，蚀刻在未形成金属膜的区域中的基板膜和基板钛膜。 因此，形成基板层（23）和基板钛层（22）。 因此，用作基板钛层（22）的基板钛膜防止由于蚀刻液体而导致的接收电极部分和各个无源元件的腐蚀，从而形成具有高性能的无源元件。

公开(公告)号：US20040221449A1

公开(公告)日：2004-11-11

申请号：US10864382

申请日：2004-06-10

Applicant: Matsushita Elec. Ind. Co. Ltd.

Inventor： Toshio Sugawa ,  Satoshi Murakawa ,  Masaaki Hayama ,  Takeo Yasuho

IPC: H05K003/40

CPC classification number: H05K3/4069 ,  H05K1/095 ,  H05K2201/0305 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/1461 ,  Y10T29/49155 ,  Y10T428/24917

Abstract: A circuit board is manufactured by filling a via-hole formed in an insulating substrate with conductive material, disposing conductive layers on both sides of the insulating substrate, and forming alloy of component material of the conductive material with component material of the conductive layers. In the circuit board, therefore, the conductive material filled in the via-hole formed in the insulating substrate is securely connected electrically as well as mechanically to the conductive layers on both sides of the insulating substrate with high reliability.

Abstract translation: 通过用导电材料填充形成在绝缘基板中的通孔来制造电路板，在绝缘基板的两侧设置导电层，以及将导电材料的组分材料的合金与导电层的成分材料形成。 因此，在电路板中，填充在形成于绝缘基板上的通路孔中的导电材料与绝缘基板两侧的导电层电连接并且机械地牢固地连接在一起，具有高可靠性。

公开(公告)号：US20040171214A1

公开(公告)日：2004-09-02

申请号：US10645478

申请日：2003-08-22

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Hiroko Koike ,  Takashi Mochizuki ,  Mitsutoshi Higashi

IPC: H01L021/8242

CPC classification number: H01L23/49822 ,  H01G9/15 ,  H01L21/4857 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0317 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2203/0315 ,  Y10S438/957 ,  Y10T29/417 ,  H01L2924/00

Abstract: A method of formation of a capacitor forming part of an electric circuit when producing a circuit board, consisting of forming a valve metal bottom electrode layer and a valve metal oxide dielectric layer on the same, then integrally forming a solid electrolyte layer comprised of an organic semiconductor and a top electrode layer comprised of metal on the same, this integral formation step consisting of the step of holding one surface of metal foil for the top electrode at a bonding wedge and making the other surface of the metal foil carry a powder of the organic semiconductor by compression bonding and heating and the step of compression bonding the organic semiconductor powder carried by compression bonding at the dielectric layer by a bonding wedge through metal foil, whereby a solid electrolyte layer comprised of an organic semiconductor sandwiched between the metal foil and dielectric layer and closely bonded with the two is formed, a capacitor built into a circuit board, a circuit board including a capacitor, and a method of production of the circuit board.

Abstract translation: 一种电容器形成电容器的形成方法，其特征在于，在制造电路基板时形成电路的一部分，其特征在于，在其上形成阀金属底电极层和阀金属氧化物电介质层，然后一体地形成由有机物构成的固体电解质层 半导体和由其上的金属组成的顶部电极层，该整体形成步骤包括将一个金属箔的表面保持在键合楔形件的顶部电极的一个表面，并使金属箔的另一个表面携带 通过压接和加热的有机半导体，以及通过金属箔通过接合楔将电介质层压接的有机半导体粉末压接的步骤，由此夹在金属箔和电介质之间的有机半导体构成的固体电解质层 形成两层紧密结合的电容器，内置于电路板的电容器，电路 其电路板包括电容器，以及生产电路板的方法。

公开(公告)号：US20040114336A1

公开(公告)日：2004-06-17

申请号：US10716143

申请日：2003-11-18

Inventor： Kevin M. Durocher ,  Richard J. Saia ,  Vikram B. Krishnamurthy

IPC: H05K001/16 ,  H05K007/06

CPC classification number: H01C17/12 ,  B29C59/14 ,  H01C7/006 ,  H05K1/0346 ,  H05K1/167 ,  H05K3/381 ,  H05K3/388 ,  H05K2201/0154 ,  H05K2201/0317 ,  H05K2203/095 ,  H05K2203/1136

Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.

公开(公告)号：US20040080021A1

公开(公告)日：2004-04-29

申请号：US10686116

申请日：2003-10-15

Inventor： Michael D. Casper ,  William B. Mraz

IPC: H01L029/00

CPC classification number: H01L21/4846 ,  H01L23/15 ,  H01L23/49822 ,  H01L25/16 ,  H01L27/016 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19011 ,  H01Q21/061 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K3/002 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H01L2924/00

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

公开(公告)号：US20040045656A1

公开(公告)日：2004-03-11

申请号：US10638668

申请日：2003-08-08

Inventor： Gwo-Ji Horng ,  Jen-I Kuo ,  Feng-Ger Hsiau

IPC: C03B029/00

CPC classification number: H01L24/32 ,  H01L21/4857 ,  H01L23/3677 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15787 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/4053 ,  H05K3/4605 ,  H05K3/4629 ,  H05K3/4679 ,  H05K2201/0317 ,  H05K2201/09063 ,  H05K2203/166 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2924/00

Abstract: A method of fabricating a thermal conductive plug of a ceramic substrate of a multi-chip package. A plurality of conductive openings and thermal conductive openings are formed on green tapes. A metal paste is filled into the conductive openings and the thermal conductive openings. The green tapes are stacked together so that the metal paste inside the conductive openings and the thermal conductive openings of every green tape is in contact respectively with its neighboring metal paste within the conductive openings and thermal conductive openings of the green tapes. Cofire those green tapes and the metal paste to form a pre-substrate. The pre-substrate comprises an insulating structure, a plurality of thermal conductive plugs and conductive plugs.

Abstract translation: 一种制造多芯片封装的陶瓷衬底的导热插塞的方法。 在绿色带上形成多个导电开口和导热开口。 将金属膏填充到导电开口和导热开口中。 生带被堆叠在一起，使得导电开口内的金属膏和每个生带的导热开口分别与导电开口内的相邻金属膏和生带的导热开口接触。 将这些绿色胶带和金属糊料烧结以形成预底物。 预衬底包括绝缘结构，多个导热插塞和导电插头。

公开(公告)号：US06661098B2

公开(公告)日：2003-12-09

申请号：US10052620

申请日：2002-01-18

Applicant: John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

Inventor： John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

IPC: H01L2348

CPC classification number: H01L24/10 ,  H01L21/67144 ,  H01L23/49811 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/34 ,  H05K3/3436 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H01L2924/00

Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

Abstract translation: 教导了通过布置在互连载体上的一组微接点互连一组器件芯片的系统。 载体具有致密阵列的具有粘附层，阻挡层和贵金属层的微接点插座; 制造器件晶片的阵列包括粘附层，阻挡层和易熔焊料层的微接合焊盘阵列，焊盘位于相对于屏障插座的匹配位置; 所述器件芯片通过微接点阵列连接到所述载体，导致能够实现非常高的输入/输出密度和芯片间布线密度的互连。