公开(公告)号：US20150085458A1

公开(公告)日：2015-03-26

申请号：US14037826

申请日：2013-09-26

Applicant: Raul Enriquez Shibayama ,  Mauro Lai ,  Richard K. Kunze ,  Nicholas B. Peterson ,  Carlos A. Lizalde Moreno ,  Kai Xiao

Inventor： Raul Enriquez Shibayama ,  Mauro Lai ,  Richard K. Kunze ,  Nicholas B. Peterson ,  Carlos A. Lizalde Moreno ,  Kai Xiao

IPC: H05K1/02 ,  H05K3/30 ,  H05K1/11

CPC classification number: H05K1/0231 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0228 ,  H05K1/115 ,  H05K1/116 ,  H05K1/162 ,  H05K3/303 ,  H05K2201/09636 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Inductive coupling arising between adjacent vias in interconnect technologies (commonly associated with printed circuit boards or package) can be combatted through the addition of metal plates to vias. The plates generate capacitive coupling that can compensate for the inductive crosstalk normally generated between vias in printed circuit boards or packages. When the added plates of two neighboring vias overlap with each other, a capacitive coupling is generated. By balancing the inductive coupling with capacitive coupling, an effective reduction of far end crosstalk may be obtained.

Abstract translation: 通过在通孔中添加金属板，互连技术中相邻通孔之间产生的感应耦合（通常与印刷电路板或封装相关联）可以对抗。 板产生电容耦合，可以补偿印刷电路板或封装中通孔之间通常产生的电感串扰。 当两个相邻通孔的添加板彼此重叠时，产生电容耦合。 通过将电感耦合与电容耦合进行平衡，可以获得远端串扰的有效减少。

公开(公告)号：US20140182891A1

公开(公告)日：2014-07-03

申请号：US14092039

申请日：2013-11-27

Applicant: Madhumitha Rengarajan ,  Jan De Geest ,  Stephen B. Smith ,  Stefaan Hendrik Jozef Sercu

Inventor： Madhumitha Rengarajan ,  Jan De Geest ,  Stephen B. Smith ,  Stefaan Hendrik Jozef Sercu

IPC: H05K1/02

CPC classification number: H05K1/116 ,  H05K1/0222 ,  H05K1/0251 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2203/0207 ,  H05K2203/0242

Abstract: In accordance with the various embodiments disclosed herein, an improved electrical connector footprint, such as on printed circuit boards (PCB), is described. For example, antipads can have a variety of sizes and pairs of differential signal traces can define centerlines that are spaced apart from each other.

Abstract translation: 根据本文公开的各种实施例，描述了改进的电连接器占用面积，例如在印刷电路板（PCB）上。 例如，反码器可以具有各种尺寸，并且差分信号迹线对可以定义彼此间隔开的中心线。

公开(公告)号：US20130326871A1

公开(公告)日：2013-12-12

申请号：US13965412

申请日：2013-08-13

Applicant: Micron Technology, Inc.

Inventor： Houfei Chen ,  Shiyou Zhao

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  G11C5/04 ,  G11C5/063 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09981 ,  H05K2203/0733 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: Substrates having power planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a first power plane and a second power plane. The at least one noise suppression structure may include a first power plane extension that extends from the first power plane generally toward the second power plane, and a second power plane extension that extends from the second power plane generally toward the first power plane. Methods for suppressing noise in at least one of the first power plane and second power plane include providing such noise suppression structures between the power planes.

Abstract translation: 具有诸如印刷电路板的电源层的衬底包括至少一个噪声抑制结构，其被配置为抑制通过第一电力平面和第二电力平面中的至少一个传播的电波。 至少一个噪声抑制结构可以包括从第一电力平面大致朝向第二电力平面延伸的第一电力平面延伸部，以及从第二电力平面大致向第一电力平面延伸的第二电力平面延伸部。 用于抑制第一电力平面和第二电力平面中的至少一个中的噪声的方法包括在电力平面之间提供这种噪声抑制结构。

公开(公告)号：US08604357B2

公开(公告)日：2013-12-10

申请号：US12501044

申请日：2009-07-10

Applicant: Tsutomu Takeda

Inventor： Tsutomu Takeda

IPC: H05K3/42 ,  H05K3/30 ,  H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0237 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09645 ,  H05K2201/09809 ,  H05K2203/0242 ,  H05K2203/175

Abstract: A wiring board has a plurality of wiring layers, a first land, a second land, a first via and a second via. The first land and the second land are formed on at least one wiring layer of the wiring board and are disposed to partially overlap with each other. The first via and the second via are formed in association with the first land and the second land, respectively. The first via and the second via electrically connect a first wiring layer and a second wiring layer of the plurality of wiring layers to each other. The wiring board has a separator that is formed by a hole that separates the first land and the second land from each other.

Abstract translation: 布线板具有多个布线层，第一片，第二片，第一片和第二片。 第一焊盘和第二焊盘形成在布线板的至少一个布线层上并且彼此部分地重叠。 第一通孔和第二通孔分别与第一焊盘和第二焊盘相关联地形成。 第一通孔和第二通孔将多个布线层中的第一布线层和第二布线层彼此电连接。 布线板具有由将第一焊盘和第二焊盘彼此分隔开的孔形成的隔板。

公开(公告)号：US08508950B2

公开(公告)日：2013-08-13

申请号：US12842637

申请日：2010-07-23

Applicant: Houfei Chen ,  Shiyou Zhao

Inventor： Houfei Chen ,  Shiyou Zhao

IPC: H05K1/18

CPC classification number: H05K1/0216 ,  G11C5/04 ,  G11C5/063 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09981 ,  H05K2203/0733 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The at least one noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Abstract translation: 具有电源和接地层的衬底，例如印刷电路板，包括至少一个噪声抑制结构，其被配置为抑制通过电力平面和接地平面中的至少一个传播的电波。 所述至少一个噪声抑制结构可以包括从所述功率平面大致朝向所述接地平面延伸的电力平面延伸部，以及从所述接地平面大致向所述电力平面延伸的接地平面延伸部。 接地平面延伸部可以与动力平面延伸部分离距离小于分离动力和接地平面的距离。 电子器件组件和系统包括这样的衬底。 用于抑制电力平面和接地平面中的至少一个中的噪声的方法包括在电源和接地层之间提供这种噪声抑制结构。

公开(公告)号：US08481866B2

公开(公告)日：2013-07-09

申请号：US13187173

申请日：2011-07-20

Applicant: Jason Edward Chan ,  Jose Ricardo Paniagua

Inventor： Jason Edward Chan ,  Jose Ricardo Paniagua

IPC: H05K1/11

CPC classification number: H01R12/523 ,  H01R12/58 ,  H01R13/6461 ,  H01R13/6477 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09845 ,  H05K2203/0242

Abstract: An electrical signal connection, an electrical signaling system, and a method of connecting printed circuit boards. The electrical signal connection having a first conductive via and a second conductive via disposed in a first printed circuit board. A first conductive trace with a first end and a second end has the first end electrically coupled to the first conductive via at a first distance from the top surface of the first printed circuit board. The second end of the first conductive via is electrically coupled to the second printed circuit board. A second conductive trace with a first end and a second end has the first end being electrically coupled to the second conductive via at a second distance from the top surface of the first printed circuit board. The second end being is electrically coupled to the second printed circuit board.

Abstract translation: 电信号连接，电信号系统和连接印刷电路板的方法。 电信号连接具有设置在第一印刷电路板中的第一导电通孔和第二导电通孔。 具有第一端和第二端的第一导电迹线具有与第一印刷电路板的顶表面第一距离处电耦合到第一导电通孔的第一端。 第一导电通孔的第二端电耦合到第二印刷电路板。 具有第一端和第二端的第二导电迹线具有第一端部，其与第一印刷电路板的顶表面距离第二距离电耦合到第二导电通孔。 第二端电连接到第二印刷电路板。

公开(公告)号：US08304662B2

公开(公告)日：2012-11-06

申请号：US11806680

申请日：2007-06-01

Applicant: Akiyoshi Saitou ,  Takeshi Midorikawa ,  Toru Kuraishi ,  Chikayuki Kumagai ,  Masashi Fujimoto ,  Kenichiro Abe

Inventor： Akiyoshi Saitou ,  Takeshi Midorikawa ,  Toru Kuraishi ,  Chikayuki Kumagai ,  Masashi Fujimoto ,  Kenichiro Abe

IPC: H05K1/16

CPC classification number: H05K1/0224 ,  H01L2924/0002 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4661 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/0959 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2203/0425 ,  H05K2203/063 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A buildup board includes a buildup layer having a multilayer structure and/or a core layer having a multilayer structure. The multilayer structure includes a signal wiring pattern, a pad connected to the signal wiring pattern, an insulating part arranged around the pad on the same layer as the pad, and a conductor arranged around the insulating part on the same layer as the pad. The multilayer structure has at least two different keepouts where the keepout is defined as a minimum interval between an outline of the pad and the conductor closest to the pad on the same layer.

Abstract translation: 堆积板包括具有多层结构的堆积层和/或具有多层结构的芯层。 多层结构包括信号布线图案，连接到信号布线图案的焊盘，与焊盘相同的层上布置在焊盘周围的绝缘部分，以及布置在与焊盘相同的层上的绝缘部分周围的导体。 所述多层结构具有至少两个不同的保持部，其中所述挡板被定义为所述焊盘的轮廓与最靠近所述焊盘在同一层上的导体之间的最小间隔。

公开(公告)号：US20120211270A1

公开(公告)日：2012-08-23

申请号：US13399107

申请日：2012-02-17

Applicant: Hideaki YOSHIMURA

Inventor： Hideaki YOSHIMURA

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/42

CPC classification number: H05K3/445 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4608 ,  H05K2201/029 ,  H05K2201/0293 ,  H05K2201/0323 ,  H05K2201/09636 ,  Y10T29/49165

Abstract: A method of manufacturing a printed wiring board includes forming a first hole penetrating a base having conductivity, closing an opening of the first hole with a film, filling an insulating material into the first hole after closing the opening, removing the film after filling the insulating material, forming a plurality of second holes penetrating the insulating material, and forming a film having conductivity on an inner surface of each of the second holes to form a plurality of wirings penetrating the insulating material.

Abstract translation: 一种制造印刷电路板的方法包括：形成贯穿具有导电性的基体的第一孔，用薄膜封闭第一孔的开口，在封闭开口之后将绝缘材料填充到第一孔中，在填充绝缘体之后除去膜 形成穿过绝缘材料的多个第二孔，并且在每个第二孔的内表面上形成具有导电性的膜，以形成穿过绝缘材料的多个布线。

公开(公告)号：US08085112B2

公开(公告)日：2011-12-27

申请号：US13187910

申请日：2011-07-21

Applicant: Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

Inventor： Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

IPC: H03H7/38

CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; the length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.

Abstract translation: 根据一个实施例，形成在多层基板中连接通孔结构和平面传输线的宽带转变，作为信号通孔焊盘和布置在相同导体层处的平面传输线之间的中间连接。 过渡的横向尺寸等于一端的通孔焊盘直径和另一端的带宽度; 转换的长度可以等于平面传输线方向上的间隙孔的特征尺寸，或者根据通过三维全波模拟获得的数字图，定义为在时域中提供极小的超额感抗 。

公开(公告)号：US08049118B2

公开(公告)日：2011-11-01

申请号：US11944813

申请日：2007-11-26

Applicant: Kazuhiro Kashiwakura

Inventor： Kazuhiro Kashiwakura

IPC: H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: Printed circuit board in which deterioration of signal transmission characteristics otherwise caused by a stub parasitically formed in a through-hole is suppressed to provide optimum high-speed signal transmission characteristics. A printed circuit board 10 includes a power supply/ground layer 11 and a signal line 12b in a dielectric layer 13, and a through-hole 12 connected to the signal line 12b. A clearance 14 which becomes an anti-pad is provided in an area between the through-hole 12 and the power supply/ground layer 11. The signal line 12b is extended from the through-hole 12 through the clearance 14 to an area below the power supply/ground layer 11. The portion of the signal line 12b arranged in the vicinity of the power supply/ground layer 11 in the clearance 14 has an area of impedance gradient 17 whose characteristic impedance becomes progressively lower in a direction away from the through-hole 12.

Abstract translation: 印刷电路板，其中抑制了由在通孔中寄生的短截线导致的信号传输特性的劣化，以提供最佳的高速信号传输特性。 印刷电路板10包括电介质层13中的电源/接地层11和信号线12b，以及连接到信号线12b的通孔12。 在通孔12和电源/接地层11之间的区域中设置成为防焊盘的间隙14.信号线12b从通孔12通过间隙14延伸到低于 电源/接地层11.布置在间隙14中的电源/接地层11附近的信号线12b的部分具有阻抗梯度17的面积，其阻抗梯度17的特征阻抗在远离通孔的方向上逐渐变小 - 孔12。