公开(公告)号：US06232560B1

公开(公告)日：2001-05-15

申请号：US09207863

申请日：1998-12-08

Applicant: Yu-Hsu Lin

Inventor： Yu-Hsu Lin

IPC: H01L2357

CPC classification number: H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0393 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

Abstract: An arrangement of printed circuit traces includes a plurality of signal and ground traces on both surfaces of a substrate alternately arranged whereby no two signal traces are adjacent to each other on the same surface and a signal trace on one surface is aligned with a ground trace on the opposite surface. The ground traces on one surface of the substrate can be replaced with power pins for a high speed signal transmission application. Alternatively, a pair of signal traces can be provided between adjacent power pins on one surface of a substrate and between adjacent ground traces on an opposite surface of the substrate. Each signal trace is formed closer to the adjacent power pin or ground trace than the adjacent signal trace. The width of each power pin and ground trace is larger than the distance between outer extremes of each pair of signal traces.

Abstract translation: 印刷电路迹线的布置包括交替布置的基板的两个表面上的多个信号和接地迹线，由此在同一表面上没有两个信号迹线彼此相邻，并且一个表面上的信号迹线与 相反的表面。 衬底的一个表面上的接地迹线可以用用于高速信号传输应用的电源引脚代替。 或者，可以在衬底的一个表面上的相邻电源引脚和衬底的相对表面上的相邻接地迹线之间提供一对信号迹线。 每个信号迹线形成为比邻近的信号迹线更靠近相邻的电源引脚或接地迹线。 每个电源引脚和接地迹线的宽度大于每对信号迹线外极点之间的距离。

公开(公告)号：US06218729B1

公开(公告)日：2001-04-17

申请号：US09267889

申请日：1999-03-11

Applicant: Robert J. Zavrel, Jr. ,  Dan C. Baumann

Inventor： Robert J. Zavrel, Jr. ,  Dan C. Baumann

IPC: H01L2304

CPC classification number: H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L25/16 ,  H01L27/0641 ,  H01L27/08 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4611 ,  H05K3/4644 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/097 ,  H05K2201/10674

Abstract: In an IC packaging scheme, a multilayer substrate is composed of electrically conductive layers of interconnects, separated by insulative layers of epoxy resin or ceramic and connected by vias. Passive elements are integrated within the substrate at the definition stage during layout of the interconnects. The passives can be used to enhance the electrical performance of the active circuit die to a maximum extent allowed by the material technology used for the substrate. Material selection for the package is made to allow for the best passive integration for a given circuit design. Typical applications include power supply bypass capacitors, radio frequency tuning, and impedance matching. The incorporation of passives in the packaging substrate creates a new class of electrically tailorable packaging that can derive improved performance for any given die design over existing approaches.

Abstract translation: 在IC封装方案中，多层基板由互连的导电层构成，由绝缘层的环氧树脂或陶瓷分隔开，并通过通孔连接。 无源元件在互连布局期间在定义阶段集成在衬底内。 无源器件可用于在用于衬底的材料技术允许的最大程度上增强有源电路管芯的电气性能。 封装的材料选择是为给定的电路设计提供了最佳的无源集成。 典型应用包括电源旁路电容，射频调谐和阻抗匹配。 无源器件在封装衬底中的并入产生了一类新的可电气封装，可以针对现有方法，为任何给定的管芯设计提供改进的性能。

公开(公告)号：US06194990B1

公开(公告)日：2001-02-27

申请号：US09268956

申请日：1999-03-16

Applicant: Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

Inventor： Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

IPC: H01C101

CPC classification number: H05K1/167 ,  H05K3/0023 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09845 ,  H05K2201/10045 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A thin-film metal resistor (44) suitable for a multilayer printed circuit board (12), and a method for its fabrication. The resistor (44) generally has a multilayer construction, with the individual layers (34, 38) of the resistor (44) being self-aligned with each other so that a negative mutual inductance is produced that very nearly cancels out the self-inductance of each resistor layer (34, 38). As a result, the resistor (44) has a very low net parasitic inductance. In addition, the multilayer construction of the resistor (44) reduces the area of the circuit board (12) required to accommodate the resistor (44), and as a result reduces the problem of parasitic interactions with other circuit elements on other layers of the circuit board (12).

Abstract translation: 适用于多层印刷电路板（12）的薄膜金属电阻（44）及其制造方法。 电阻器（44）通常具有多层结构，其中电阻器（44）的各个层（34,38）彼此自对准，使得产生负的互感，其几乎抵消了自感 的每个电阻层（34,38）。 结果，电阻器（44）具有非常低的净寄生电感。 此外，电阻器（44）的多层结构减小了容纳电阻器（44）所需的电路板（12）的面积，结果减少了与其他层上的其它电路元件的寄生相互作用的问题 电路板（12）。

公开(公告)号：US5986893A

公开(公告)日：1999-11-16

申请号：US83891

申请日：1998-05-21

Applicant: Kevin B. Leigh ,  Michael Y. Chan

Inventor： Kevin B. Leigh ,  Michael Y. Chan

IPC: H05K1/02 ,  H05K7/02

CPC classification number: H05K1/0228 ,  H05K1/0219 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/10689

Abstract: The present invention relates to the placement of signal traces on a two-sided printed circuit board such that impedance of the traces is controlled and so that the number of power and ground pins required on an integrated circuit are minimized.

Abstract translation: 本发明涉及将信号迹线放置在双面印刷电路板上，使得迹线的阻抗被控制，使得集成电路上所需的功率和接地引脚的数量最小化。

公开(公告)号：US5978222A

公开(公告)日：1999-11-02

申请号：US924958

申请日：1997-09-08

Applicant: Makoto Iijima ,  Tetsushi Wakabayashi ,  Toshio Hamano ,  Masaharu Minamizawa ,  Masashi Takenaka ,  Taturou Yamashita ,  Masataka Mizukoshi

Inventor： Makoto Iijima ,  Tetsushi Wakabayashi ,  Toshio Hamano ,  Masaharu Minamizawa ,  Masashi Takenaka ,  Taturou Yamashita ,  Masataka Mizukoshi

IPC: H01L23/12 ,  H01L21/48 ,  H01L21/60 ,  H01L23/10 ,  H01L23/14 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H05K3/46 ,  H05T7/20

CPC classification number: H01L24/81 ,  H01L21/486 ,  H01L23/10 ,  H01L23/142 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H05K3/4602 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K2201/0959 ,  H05K2201/09672

Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.

公开(公告)号：US5972231A

公开(公告)日：1999-10-26

申请号：US962065

申请日：1997-10-31

Applicant: Joseph T. DiBene, II

Inventor： Joseph T. DiBene, II

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  B44C1/22

CPC classification number: H05K1/162 ,  H05K1/0237 ,  H05K1/0239 ,  H05K1/0298 ,  H05K2201/09381 ,  H05K2201/09672

Abstract: A method and apparatus for coupling high speed data components using imbedded PCB AC coupling capacitors is disclosed. The capacitor comprises a first and a second conductive plate of polygonal shape coupled to surrounding circuitry at the polygonal vertices of the polygonal plates. This configuration results in improved capacitor performance, particularly with respect to capacitive impedance and reflected waves for high bandwidth signals at the frequency ranges of interest.

Abstract translation: 公开了一种使用嵌入式PCB AC耦合电容器耦合高速数据组件的方法和装置。 电容器包括多边形形状的第一和第二导电板，其耦合到多边形板的多边形顶点处的周围电路。 该配置导致改善的电容器性能，特别是关于在感兴趣的频率范围上的高带宽信号的电容阻抗和反射波。

公开(公告)号：US5749049A

公开(公告)日：1998-05-05

申请号：US18132

申请日：1993-02-16

Applicant: Nicholas Jacob Worp

Inventor： Nicholas Jacob Worp

IPC: H04B5/00 ,  H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  H04B17/00

CPC classification number: H04B5/04 ,  H04B5/0012 ,  H05K1/162 ,  H05K1/0268 ,  H05K1/0298 ,  H05K2201/09672

Abstract: An electronic device includes a substrate (200) for supporting electrical circuits (202), the substrate (200) including first and second opposing surface areas (204 and 206). At least first and second electrical contacts (214 and 216) are disposed on the substrate 200 and are electrically coupled to at least first and second conductive plates (210 and 212), respectively. The first and second conductive plates (210 and 212) are disposed on the first and second opposing surface areas (204 and 206) of the substrate (200), respectively. Preferably, the first and second conductive plates (210 and 212) at least partially overlap with each other. The first and second conductive plates (210 and 212) form a capacitive element therebetween for determining excessive variability in composition of the substrate as indicated by a measured inherent capacitance of the substrate at the capacitive element that is outside a specified tolerance of the capacitive element (200).

Abstract translation: 电子设备包括用于支撑电路（202）的基板（200），所述基板（200）包括第一和第二相对表面区域（204和206）。 至少第一和第二电触头（214和216）分别设置在基板200上并分别电耦合到至少第一和第二导电板（210和212）。 第一和第二导电板（210和212）分别设置在基板（200）的第一和第二相对表面区域（204和206）上。 优选地，第一和第二导电板（210和212）至少部分地彼此重叠。 第一和第二导电板（210和212）在其间形成电容元件，用于确定衬底的组成的过度变化，如电容元件处的衬底在电容元件的规定公差之外的测量的固有电容所示（ 200）。

公开(公告)号：US5729435A

公开(公告)日：1998-03-17

申请号：US782381

申请日：1997-01-13

Applicant: Makoto Iijima ,  Tetsushi Wakabayashi ,  Toshio Hamano ,  Masaharu Minamizawa ,  Masashi Takenaka ,  Taturou Yamashita ,  Masataka Mizukoshi

Inventor： Makoto Iijima ,  Tetsushi Wakabayashi ,  Toshio Hamano ,  Masaharu Minamizawa ,  Masashi Takenaka ,  Taturou Yamashita ,  Masataka Mizukoshi

IPC: H01L23/12 ,  H01L21/48 ,  H01L21/60 ,  H01L23/10 ,  H01L23/14 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H05K3/46 ,  H05K7/20

CPC classification number: H01L24/81 ,  H01L21/486 ,  H01L23/10 ,  H01L23/142 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H05K3/4602 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K2201/0959 ,  H05K2201/09672

Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, and an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths. The semiconductor device further includes a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a passage restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.

Abstract translation: 半导体器件包括具有填充有填充芯的通孔的板基板和设置在基板的上表面上的添加层以及填充芯的上表面，其中添加层包括具有一个的布线图案 或更多路径。 半导体装置还包括固定在该添加层的上表面上的半导体芯片和设置在该基板的下表面上的节点，其中，一条或多条路径被布置而没有由通孔所引起的通道限制， 并用于电连接半导体芯片和节点。

公开(公告)号：US5527999A

公开(公告)日：1996-06-18

申请号：US391740

申请日：1995-02-21

Applicant: Bradley R. Knigga ,  Christine A. Paszkiet

Inventor： Bradley R. Knigga ,  Christine A. Paszkiet

IPC: H01L23/538 ,  H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K1/0265 ,  H01L23/5383 ,  H01L2924/0002 ,  H05K1/092 ,  H05K1/115 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K3/4664

Abstract: A multilayer circuit is provided characterized by a multilayer conductor structure. The multilayer conductor structure is composed of at least two conductor layers, with each adjacent layer being separated by a dielectric material in the form of one or more dielectric layers. The multilayer circuit further includes electrically conductive members or features for electrically interconnecting the conductor layers at two or more locations along the lengths of the conductor layers. As a result, portions of the conductor layers between two or more locations are electrically in parallel with each other, such that the multilayer conductor is characterized by an electrical resistance between the locations which is less than the electrical resistance of the individual conductor layers between the locations. The multilayer conductor is therefore characterized by an augmented current-carrying capacity as compared to a single layer conductor of the same length and width.

Abstract translation: 提供了一种多层电路，其特征在于多层导体结构。 多层导体结构由至少两个导体层组成，每个相邻层由一个或多个介电层形式的电介质材料隔开。 多层电路还包括导电构件或特征，用于沿着导体层的长度在两个或更多个位置处电连接导体层。 结果，两个或更多个位置之间的导体层的部分彼此电并联，使得多层导体的特征在于小于单个导体层之间的电阻的位置之间的电阻 位置。 因此，与具有相同长度和宽度的单层导体相比，多层导体的特征在于增大的载流能力。

公开(公告)号：US5466892A

公开(公告)日：1995-11-14

申请号：US13076

申请日：1993-02-03

Applicant: James R. Howard ,  Gregory L. Lucas

Inventor： James R. Howard ,  Gregory L. Lucas

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/16

CPC classification number: H05K1/162 ,  H05K1/0239 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/09672 ,  H05K2201/10689

Abstract: A circuit board and method of forming a circuit board with signal and receptor pads arranged on layers spaced apart in a Z direction with a dielectric layer therebetween, parameters of a resulting AC signal transmitting circuit resulting wherein:capacitive reactance is defined by the equation (I) ##EQU1## where F is frequency and C is capacitance; inductive reactance is defined by the equation (II)X.sub.L =2.pi.FLwhere F is frequency and L is inductance;capacitance is defined by the equation (III) ##EQU2## where A is the effective mutual area of the signal and receptor pads, D is Faraday's constant, E is the dielectric constant, and .tau. is the thickness of the dielectric layer; andinductance is defined by the equation (IV)L=0.005 ln (4h/d).mu.H/in.where ln indicates the natural logarithm for the value 4h/d, where h is the distance above a ground plane, and d is the equivalent diameter of a conductor;wherein capacitance and inductance are established in equations I and II with X.sub.C and X.sub.L being equal or approaching equality and the values of A, D, .tau., I.sub.N, h (etc.) are preselected or calculated from equations III and IV.

Abstract translation: 一种电路板和形成电路板的方法，其中信号和接收垫布置在Z方向间隔开的介质层之间，其间具有介电层，得到的AC信号传输电路的参数得到：其中：容抗由公式（I ）ce 感抗由等式（II）XL = 2 pi FL定义，其中F是频率，L是电感; 电容由等式（III）定义，其中A是信号和接收垫的有效相互面积，D是法拉第常数，E是介电常数，τ是介电层的厚度; 电感由方程式（Ⅳ）定义，L = 0.005 ln（4h / d）μH/ in。 其中ln表示值4h / d的自然对数，其中h是接地平面上方的距离，d是导体的当量直径; 其中电容和电感在等式I和II中用XC和XLbeing等于或接近相等建立，并且A，D，τ，IN，h（等）的值由等式III和IV预选或计算。