公开(公告)号：US20020073282A1

公开(公告)日：2002-06-13

申请号：US09932651

申请日：2001-08-17

Inventor： Gerard Chauvel ,  Maija Kuusela ,  Dominique D'Inverno ,  Serge Lasserre

IPC: G06F012/08

CPC classification number: G06F9/5011 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/30043 ,  G06F9/5094 ,  G06F11/3409 ,  G06F12/0292 ,  G06F12/0879 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1081 ,  G06F2201/81 ,  G06F2201/815 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2209/5014 ,  G06F2209/5021 ,  G06F2209/507 ,  G06F2212/1028 ,  G06F2212/681 ,  Y02D10/13 ,  Y02D10/16 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/34

Abstract: A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. When the L2-cache misses, the penalty to access to data within the L3 memory is high. The system supports miss under miss to let a second miss interrupt a segment prefetch being done in response to a first miss. Thus, an interruptible SDRAM to L2-cache prefetch system with miss under miss support is provided. A shared translation look-aside buffer (TLB) is provided for L2 accesses, while a private TLB is associated with each processor. A micro TLB (nullTLB) is associated with each resource that can initiate a memory transfer. The L2 cache, along with all of the TLBs and nullTLBs have resource ID fields and task ID fields associated with each entry to allow flushing and cleaning based on resource or task. Configuration circuitry is provided to allow the digital system to be configured on a task by task basis in order to reduce power consumption.

Abstract translation: 数字系统具有几个处理器，与每个处理器相关联的私有一级（L1）高速缓存，每个条目具有多个段的共享二级（L2）高速缓存以及三级（L3）物理存储器。 共享的L2高速缓存体系结构体现为4路关联性，每个条目有4个段和4个有效位和脏位。 当L2缓存未命中时，访问L3内存中的数据的惩罚很高。 该系统支持未命中错过，以使第二个错误中断一个段预取正在响应于第一个错过。 因此，提供了一个可中断的SDRAM到L2缓存预取系统，其中错过了支持。 为L2访问提供共享翻译后备缓冲器（TLB），而私有TLB与每个处理器相关联。 微型TLB（muTLB）与可以启动存储器传输的每个资源相关联。 L2缓存以及所有TLB和muTLB都具有与每个条目关联的资源ID字段和任务ID字段，以允许基于资源或任务的冲洗和清理。 提供配置电路以允许数字系统根据任务在任务上进行配置，以便降低功耗。

公开(公告)号：US20020069339A1

公开(公告)日：2002-06-06

申请号：US09932807

申请日：2001-08-17

Inventor： Serge Lasserre ,  Gerard Chauvel ,  Dominique D'Inverno

IPC: G06F012/10

CPC classification number: G06F9/30043 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F12/0292 ,  G06F12/0879 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1081 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/24

Abstract: A digital system is provided with a memory (506) shared by several initiator resources (540-550), wherein a portion of the initiator resources are big endian and another portion of the initiator resources are little endian. The memory is segregated into a set of regions by a memory management unit (MMU) (500-510) and an endianism attribute bit is defined for each region. For each memory request to the memory, the endianism attribute bit for the selected region is provided by the MMU. Each memory transaction request is completed in accordance with the endianism attribute of the selected region. Depending on the capability of a given initiator resource, the memory request address is adjusted to agree with the endianism attribute of the selected region, or an access fault is generated (530) if the endianism of the initiating resource does not match the endianism attribute of the selected memory region. A resource identification value (R-ID) provided by each of the initiator resources is used to identify the endianism of each of the initiator resources.

Abstract translation: 数字系统具有由几个发起者资源（540-550）共享的存储器（506），其中一部分发起者资源是大端，另一部分发起者资源是小端。 存储器通过存储器管理单元（MMU）（500-510）分离成一组区域，并且为每个区域定义一个endianistic属性位。 对于存储器的每个存储器请求，MMU提供所选区域的endianistic属性位。 每个存储器事务请求都是根据所选区域的endianism属性完成的。 根据给定的启动器资源的能力，调整存储器请求地址以与所选区域的endianism属性一致，或者如果启动资源的endianism不匹配于endianism属性，则生成访问错误（530） 所选存储区域。 由每个启动器资源提供的资源标识值（R-ID）用于识别每个发起者资源的端点。

公开(公告)号：US20020069332A1

公开(公告)日：2002-06-06

申请号：US09932794

申请日：2001-08-17

Inventor： Gerard Chauvel ,  Serge Lasserre

IPC: G06F012/08

CPC classification number: G06F9/30043 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F12/0292 ,  G06F12/0835 ,  G06F12/0879 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1081 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/24

Abstract: A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). A single global validity circuit (VIG) is connected to the memory circuit and is operable to indicate if any segment of the multiple segments holds valid data. Block transfer circuitry (700, 702) is connected to the memory circuit and is operable to transfer a block of data (1650) to a selected portion of segments (1606) of the cache memory circuit. The block circuitry is operable to transfer data from a pre-selected region of the secondary memory (1650) to a particular segment of the plurality of segments and to assert the global valid bit at the completion of a block transfer. Direct memory access (DMA) circuitry (1610) is connected to the memory cache for transferring data between the memory cache and a selectable region (1650) of a secondary memory and is also operable to assert the global valid bit at the completion of a DMA block transfer. The cache can be operated in a first manner such that when a transfer request from the processor requests a first location in the cache memory that does not hold valid data, valid data is transferred (1652) from a pre-selected location in a secondary memory that corresponds directly to the first location. The cache can then be operated in a second manner such that data is transferred (1662) between the first location and a selectable location in the secondary memory, wherein the selected location need not directly correspond to the first location.

Abstract translation: 提供了一种数字系统和操作方法，其中数字系统具有至少一个处理器，具有相关联的多段高速缓存存储器电路（506（n）），单个全局有效性电路（VIG）连接到存储器电路， 块传输电路（700,702）连接到存储器电路，并且可操作以将数据块（1650）传送到片段（1606）的选定部分， 块电路可操作以将数据从辅助存储器（1650）的预先选择的区域传送到多个段的特定段，并且在块传送完成时断言全局有效位 直接存储器访问（DMA）电路（1610）连接到存储器高速缓存，用于在存储器高速缓存和辅助存储器的可选择区域（1650）之间传送数据，并且还可操作以在补充存储器中断言全局有效位 DMA块传输。 高速缓存可以以第一方式操作，使得当来自处理器的传送请求请求高速缓冲存储器中不保存有效数据的第一位置时，有效数据从副存储器中的预先选择的位置传送（1652） 它直接对应于第一个位置。 然后可以以第二方式操作高速缓存，使得数据在辅助存储器中的第一位置和可选位置之间传送（1662），其中所选择的位置不需要直接对应于第一位置。

公开(公告)号：US20020062409A1

公开(公告)日：2002-05-23

申请号：US09932650

申请日：2001-08-17

Inventor： Serge Lasserre ,  Gerard Chauvel

IPC: G06F012/08

CPC classification number: G06F9/30043 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F12/0292 ,  G06F12/0835 ,  G06F12/0862 ,  G06F12/0879 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1081 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/24

Abstract: A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block transfer circuitry (700, 702) is connected to the memory circuit and is operable to transfer a block of data (1650) to a selected portion of segments (1606) of the cache memory circuit. Fetch circuitry associated with the memory cache is operable to transfer data from a pre-selected region of the secondary memory (1650) to a particular segment of the plurality of segments and to assert a first valid bit corresponding to the segment when the miss detection circuitry (1610) detects a miss in the segment. Direct memory access (DMA) circuitry (1610) is connected to the memory cache for transferring data between the memory cache and a selectable region (1650) of a secondary memory. The cache can be operated in a first manner such that when a transfer request from the processor requests a first location in the cache memory that does not hold valid data, valid data is transferred (1652) from a pre-selected location in a secondary memory that corresponds directly to the first location. The cache can then be operated in a second manner such that data is transferred (1662) between the first location and a selectable location in the secondary memory, wherein the selected location need not directly correspond to the first location.

Abstract translation: 提供了一种数字系统和操作方法，其中数字系统具有至少一个具有相关联的多段高速缓冲存储器电路（506（n））的处理器，有效电路（VI）连接到存储器电路，并且可操作以 块传输电路（700,702）连接到存储器电路，并且可操作以将数据块（1650）传送到所述多个段的片段（1606）的选定部分 与存储器高速缓存相关联的获取电路可操作以将数据从辅助存储器（1650）的预先选择的区域传送到多个段的特定段，并且当对应于该段的第一有效位时 未命中检测电路（1610）检测该片段中的未命中，直接存储器访问（DMA）电路（1610）连接到存储器高速缓存，用于在存储器高速缓存和可选区域（1650）之间传送数据 第一记忆 高速缓存可以以第一方式操作，使得当来自处理器的传送请求请求高速缓冲存储器中不保存有效数据的第一位置时，有效数据从副存储器中的预先选择的位置传送（1652） 它直接对应于第一个位置。 然后可以以第二方式操作高速缓存，使得数据在辅助存储器中的第一位置和可选位置之间传送（1662），其中所选择的位置不需要直接对应于第一位置。

公开(公告)号：US20020046204A1

公开(公告)日：2002-04-18

申请号：US09938151

申请日：2001-08-23

Inventor： Scott R. Hayes

IPC: G06F007/00

CPC classification number: G06F11/3409 ,  G06F11/3414 ,  G06F11/3452 ,  G06F16/22 ,  G06F2201/80 ,  G06F2201/81 ,  G06F2201/885

Abstract: The present invention is a method for automating database bufferpool tuning for optimized performance that employs certain heuristic algorithms to achieve its goals. Over a period of time, memory (bufferpool) performance is measured and accumulated in a repository. The repository becomes a knowledge base that is accessed by the algorithms and the ideal memory (bufferpool) configurations, which optimize database performance, are learned and implemented. The sampling of performance continues at regular intervals and the knowledge base continues to grow. As knowledge continues to accumulate, the algorithms are forbidden from becoming complacent. The ideal bufferpool memory configurations are regularly reevaluated to ensure they continue to be optimal given potential changes in the database's use or access patterns.

Abstract translation: 本发明是一种用于自动化数据库缓冲池调整以优化性能的方法，其采用某些启发式算法来实现其目标。 在一段时间内，内存（缓冲池）性能被测量并在存储库中累积。 存储库成为通过算法访问的知识库，并且学习和实现了优化数据库性能的理想内存（缓冲池）配置。 绩效抽样定期继续，知识基础继续增长。 随着知识的不断积累，算法被禁止变得自满。 定期重新评估理想的缓冲池内存配置，以确保数据库的使用或访问模式发生潜在变化，从而保持最佳化。

公开(公告)号：US06345337B1

公开(公告)日：2002-02-05

申请号：US09440727

申请日：1999-11-16

Applicant: Bruce McNutt ,  David Alastair Short ,  Brian Jay Smith

Inventor： Bruce McNutt ,  David Alastair Short ,  Brian Jay Smith

IPC: G06F1212

CPC classification number: G06F11/3419 ,  G06F11/3452 ,  G06F12/12 ,  G06F2201/885

Abstract: A method for determining a single reference residency time of a cache comprises the steps of causing test data to be staged to the cache and measuring a response time after a wait time has elapsed. The measuring step is repeated for a plurality of values of wait time. The method also includes the step of determining a boundary value of the wait time. A wait time of less than or equal to the boundary value yields a corresponding response time representing a cache hit and a wait time of greater than the boundary value yields a corresponding response time representing a cache miss. The boundary value is an estimate of the single reference residency time of the cache.

Abstract translation: 一种用于确定高速缓存的单个引用驻留时间的方法包括以下步骤：使测试数据分段到高速缓存并且在经过等待时间之后测量响应时间。 针对多个等待时间值重复测量步骤。 该方法还包括确定等待时间的边界值的步骤。 小于或等于边界值的等待时间产生表示高速缓存命中的对应响应时间，并且大于边界值的等待时间产生表示高速缓存未命中的对应响应时间。 边界值是缓存的单个引用驻留时间的估计。

公开(公告)号：US20020013938A1

公开(公告)日：2002-01-31

申请号：US09755381

申请日：2001-01-05

Inventor： Evelyn Duesterwald ,  Vasanth Bala ,  Sanjeev Banerjia

IPC: G06F009/45

CPC classification number: G06F9/45504 ,  G06F8/4435 ,  G06F9/3832 ,  G06F11/3471 ,  G06F11/3476 ,  G06F2201/81 ,  G06F2201/88 ,  G06F2201/885

Abstract: A link-time optimization scheme is capable of removing from dead code from code fragments in a program which arise after the linking of code fragments. The scheme may be applied runtime to fragments which are linked in a caching dynamic translator or applied when linking fragments subsequent to the compilation of object code. The removal of dead code may be facilitated by the use of epilogs corresponding to exits from a fragment and prologs corresponding to entries into a fragment.

Abstract translation: 链路时间优化方案能够从代码片段链接之后产生的程序中的代码片段中删除死码。 该方案可以应用于在缓存动态翻译器中链接的片段，或者在编译目标代码之后链接片段时应用。 可以通过使用对应于来自片段的出口的epilog和对应于片段中的条目的序列来促进删除死代码。

公开(公告)号：US06308210B1

公开(公告)日：2001-10-23

申请号：US09210132

申请日：1998-12-10

Applicant: Duane Kimbell Fields ,  Thomas Preston Gregg ,  Sebastian Hassinger ,  William Walter Hurley, II

Inventor： Duane Kimbell Fields ,  Thomas Preston Gregg ,  Sebastian Hassinger ,  William Walter Hurley, II

IPC: G06F1130

CPC classification number: G06F11/3438 ,  G06F2201/875 ,  G06F2201/885

Abstract: The invention is used to balance and control traffic within a single internet site or between multiple sites. A static or dynamic analysis of site usage is performed. When an under-visited portion of a site is identified, then a link or message is created on a more-visited portion of the web-site to motivate the user visiting the site to explore the under-visited portion. The portion can be a specific page of the web site, or an entire section.

Abstract translation: 本发明用于平衡和控制单个互联网站点内或多个站点之间的流量。 执行站点使用的静态或动态分析。 当识别出站点的未被访问的部分时，则在网站的更多访问部分上创建链接或消息，以激励访问该站点的用户探索未被访问的部分。 该部分可以是网站的特定页面，也可以是整个部分。

公开(公告)号：US06295608B1

公开(公告)日：2001-09-25

申请号：US09024857

申请日：1998-02-17

Applicant: Michael Andrew Brian Parkes ,  Barry Michael Nolte ,  Douglas Stewart Boa

Inventor： Michael Andrew Brian Parkes ,  Barry Michael Nolte ,  Douglas Stewart Boa

IPC: H02H305

CPC classification number: G06F8/4441 ,  G06F11/3466 ,  G06F2201/885 ,  Y10S707/99953 ,  Y10S707/99954

Abstract: An invention for reassigning data elements of an application to cache lines to decrease the occurrence of cache line faults is described. First, an application is executed and used in a typically manner. While the application is running, data is collected concerning the loading and storing of data elements. This collection process creates a massive volume of data that is then processed to determine correlations between the loading and storing pairs of elements within each of the application's data structures. These correlations provide a mechanism for weighing the probability of pairs of intra-structure data elements being accessed in sequence, which is best accomplished when the data elements are within a single cache line. A set of simultaneous equations describe the probabilities using the data recording the correlations. These equations are then solved using commonly known linear programming techniques to derive a suggested ordering of data structures. An interactive editor is then used to reorder these data elements in the derived preferred order as authorized by the programmer.

Abstract translation: 描述了用于将应用的数据元素重新分配到高速缓存行以减少高速缓存线路故障的发生的发明。 首先，应用程序以典型的方式执行和使用。 当应用程序运行时，收集关于数据元素的加载和存储的数据。 此收集过程创建大量数据，然后处理数据，以确定每个应用程序的数据结构中的加载和存储对元素之间的相关性。 这些相关性提供了一种用于称量顺序地访问的结构内数据元素对的概率的机制，当数据元素在单个高速缓存行内时，这是最佳实现的。 一组联立方程使用记录相关性的数据描述概率。 然后使用公知的线性规划技术来解决这些方程，以得出建议的数据结构排序。 然后，交互式编辑器用于按照程序员的授权对派生优选顺序中的这些数据元素进行重新排序。

公开(公告)号：US06282570B1

公开(公告)日：2001-08-28

申请号：US09206503

申请日：1998-12-07

Applicant: Tony Kai-Chi Leung ,  Siu Nang See ,  Stan Wong ,  Cheung-Yuk Wu

Inventor： Tony Kai-Chi Leung ,  Siu Nang See ,  Stan Wong ,  Cheung-Yuk Wu

IPC: G06F1314

CPC classification number: G06F11/3409 ,  G06F11/3452 ,  G06F11/3495 ,  G06F2201/80 ,  G06F2201/835 ,  G06F2201/885 ,  Y10S707/99952

Abstract: The present invention discloses a method, apparatus, and article of manufacture for monitoring performance of a parallel database in a computer. In accordance with the present invention, the parallel database is stored on a data storage device in the computer. Groups of database nodes are identified. Collection time periods for collecting performance statistics from the identified group of database nodes are determined. Performance statistics are periodically collected from a subset of each identified group of nodes during the collection time periods. The collected performance statistics are stored in a memory connected to the computer and re-used when collecting performance statistics from one or more groups of database nodes in a succeeding collection time period.

Abstract translation: 本发明公开了一种用于监视计算机中的并行数据库的性能的方法，装置和制品。 根据本发明，并行数据库被存储在计算机中的数据存储装置上。 识别数据库节点组。 确定从识别的数据库节点组收集性能统计信息的收集时间段。 在收集时间段期间，每个确定的节点组的子集定期收集性能统计信息。 收集的性能统计信息存储在连接到计算机的存储器中，并在后续采集时间段内从一个或多个数据库节点组收集性能统计信息时重新使用。