公开(公告)号：US08117744B2

公开(公告)日：2012-02-21

申请号：US13027167

申请日：2011-02-14

Applicant: Michael Nashner ,  Jeffrey Howerton

Inventor： Michael Nashner ,  Jeffrey Howerton

IPC: H01K3/10

CPC classification number: H05K3/445 ,  H05K1/053 ,  H05K3/4061 ,  H05K5/0247 ,  H05K2201/0179 ,  H05K2201/09581 ,  H05K2201/09827 ,  H05K2203/0315 ,  H05K2203/0323 ,  H05K2203/107 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of forming an isolated electrically conductive contact through a metallic substrate includes creating at least one via through the substrate, where the via includes a first opening in a top surface of the substrate, a second opening in an opposing bottom surface and at least one continuous sidewall extending therebetween. A dielectric sleeve is formed on the at least one sidewall of the via while preserving at least a portion of the through via. An electrically conductive filler is then placed into the via. In the examples disclosed, the filler may be a conductive ink or a conductive epoxy.

Abstract translation: 通过金属基底形成隔离的导电接触的方法包括产生穿过基底的至少一个通孔，其中通孔包括在基底的顶表面中的第一开口，在相对的底表面中的第二开口和至少一个 连续的侧壁在其间延伸。 介电套筒形成在通孔的至少一个侧壁上，同时保留通孔的至少一部分。 然后将导电填料放入通孔中。 在所公开的实施例中，填料可以是导电油墨或导电环氧树脂。

公开(公告)号：US20110102122A1

公开(公告)日：2011-05-05

申请号：US12985475

申请日：2011-01-06

Applicant: Yasuhiko MANO ,  Takashi KARIYA ,  Shinobu KATO

Inventor： Yasuhiko MANO ,  Takashi KARIYA ,  Shinobu KATO

IPC: H01F5/00 ,  H05K3/00

CPC classification number: H05K3/4046 ,  H01F17/0006 ,  H01F17/06 ,  H01F41/046 ,  H01F2017/002 ,  H01F2017/065 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0233 ,  H05K1/115 ,  H05K1/185 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09581 ,  Y10T29/4902 ,  H01L2224/05599

Abstract: A printed wiring board including a substrate having a first surface and a second surface on the opposite side of the second surface, a first conductive circuit formed on the first surface of the substrate, a second conductive circuit formed on the second surface of the substrate, a magnetic body embedded in the substrate and extending in a thickness direction of the substrate, the magnetic body having a through-hole formed through the magnetic body and extending in the thickness direction of the substrate, and a through-hole conductor formed on an inner surface of the through-hole of the magnetic body such that the first and second conductive circuits are electrically connected to each other through the through-hole conductor.

Abstract translation: 一种印刷电路板，包括具有在所述第二表面的相对侧上的第一表面和第二表面的基板，形成在所述基板的第一表面上的第一导电电路，形成在所述基板的第二表面上的第二导电电路， 磁性体，其嵌入到所述基板中并沿着所述基板的厚度方向延伸，所述磁性体具有通过所述磁性体形成并在所述基板的厚度方向上延伸的通孔，以及形成在所述基板的内部的通孔导体 磁体的通孔的表面，使得第一和第二导电电路通过通孔导体彼此电连接。

公开(公告)号：US20110035939A1

公开(公告)日：2011-02-17

申请号：US12708280

申请日：2010-02-18

Applicant: Toshiaki MORI ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

Inventor： Toshiaki MORI ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

IPC: H05K3/00

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/0366 ,  H05K1/162 ,  H05K3/0041 ,  H05K3/0044 ,  H05K3/388 ,  H05K3/4061 ,  H05K3/4069 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/09763 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/1338 ,  H05K2203/1581 ,  Y10T29/43 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

Abstract translation: 在层叠在所述芯板的一个表面上的芯板，布线层和电绝缘层的多层布线基板中，所述芯板的XY方向的热膨胀系数在2〜20ppm的范围内 所述芯板的核心部件是选自硅，陶瓷，玻璃，玻璃 - 环氧复合材料和金属的核心部件，所述芯板设置有多个在正面和背面之间导电的通孔 通过导电材料，并且在所述芯板的一个表面上设置电容器，其中所述电容器包括在所述通孔中作为导电材料的上电极和设置成经由电介质层面对所述上电极的下电极 。

公开(公告)号：US07868728B2

公开(公告)日：2011-01-11

申请号：US12692907

申请日：2010-01-25

Applicant: Yasuhiko Mano ,  Takashi Kariya ,  Shinobu Kato

Inventor： Yasuhiko Mano ,  Takashi Kariya ,  Shinobu Kato

IPC: H01F5/00

CPC classification number: H05K3/4046 ,  H01F17/0006 ,  H01F17/06 ,  H01F41/046 ,  H01F2017/002 ,  H01F2017/065 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0233 ,  H05K1/115 ,  H05K1/185 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09581 ,  Y10T29/4902 ,  H01L2224/05599

Abstract: An inductor embedded in a printed wiring board includes a conductor extending in the thickness direction of a printed circuit board and a magnetic body that is in contact with the conductor with no gap therebetween. For example, the magnetic body is composed of ferrite having a cylindrical tubular shape. The conductor is composed of a copper film formed by plating on an inner peripheral surface of the cylindrical tubular ferrite. The inductor is inserted in the thickness direction of the printed wiring board.

Abstract translation: 嵌入印刷电路板的电感器包括沿着印刷电路板的厚度方向延伸的导体和与导体接触而不间隙的磁体。 例如，磁性体由具有圆柱形管状的铁氧体构成。 导体由在圆筒形管状铁氧体的内周面上电镀形成的铜膜构成。 电感器沿印刷电路板的厚度方向插入。

公开(公告)号：US20100326716A1

公开(公告)日：2010-12-30

申请号：US12459082

申请日：2009-06-26

Applicant: Zhichao Zhang ,  Kemal Aygun ,  Guizhen Zheng

Inventor： Zhichao Zhang ,  Kemal Aygun ,  Guizhen Zheng

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K1/024 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/4038 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09581 ,  Y10T29/49155

Abstract: In integrated circuit packages, core vias are created to provide electrical connections between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods for forming a via in a packaging substrate and packaging substrates having core vias formed in the core substrate material. Methods for forma a core via in a packaging substrate in which a first hole is created through the core substrate and filled with a low permittivity filler material. A second co-axially aligned hole is then created in the low permittivity filler material wherein the second hole is smaller in diameter than the first hole. The second hole is then filled with conducting material to provide a conducting via through the core substrate material.

Abstract translation: 在集成电路封装中，形成核心通孔以在芯基板材料的一个面上的电路与芯基板材料的相对面上的电路之间提供电连接。 提供了在封装基板中形成通孔的方法以及在芯基板材料中形成有芯通孔的封装基板。 在包装基材中形成芯通孔的方法，其中通过芯基板产生第一孔并填充低介电常数的填充材料。 然后在低介电常数填充材料中产生第二同轴对准的孔，其中第二孔的直径小于第一孔。 然后用导电材料填充第二孔，以通过芯基板材料提供导电通孔。

公开(公告)号：US07772118B2

公开(公告)日：2010-08-10

申请号：US12061768

申请日：2008-04-03

Applicant: Takaharu Yamano

Inventor： Takaharu Yamano

IPC: H01L21/44 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1461 ,  H05K1/0306 ,  H05K3/007 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4605 ,  H05K3/4661 ,  H05K2201/0236 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0723 ,  H05K2203/0733 ,  H05K2203/1105 ,  H05K2203/1383 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A disclosed substrate is composed of a base member having a through-hole, a penetrating via provided in the through-hole, and a wiring connected to the penetrating via. The penetrating via includes a penetrating part having two ends on both sides of the base member, which is provided in the through-hole, a first protrusion protruding from the base member, which is formed on a first end of the penetrating part so as to be connected to the wiring, and a second protrusion protruding from the base member, which is formed on a second end of the penetrating part. The first protrusion and second protrusion are wider than a diameter of the through-hole.

Abstract translation: 所公开的基板由具有通孔的基部构件，设置在通孔中的贯通孔以及与贯通孔连接的配线构成。 贯通孔包括贯通部，该贯通部在基部构件的两侧设置有设置在贯通孔中的两端，从基体突出的第一突起，该第一突起形成在贯通部的第一端上，从而 连接到布线，以及形成在穿透部的第二端上的从基部构件突出的第二突起。 第一突起和第二突起比通孔的直径宽。

公开(公告)号：US07679004B2

公开(公告)日：2010-03-16

申请号：US10598524

申请日：2005-03-02

Applicant: Katsuya Fukase ,  Toyoaki Sakai ,  Munetoshi Irisawa ,  Toyokazu Komuro ,  Yasuo Kaneda ,  Masanori Natsuka ,  Wakana Aizawa

Inventor： Katsuya Fukase ,  Toyoaki Sakai ,  Munetoshi Irisawa ,  Toyokazu Komuro ,  Yasuo Kaneda ,  Masanori Natsuka ,  Wakana Aizawa

IPC: H01R12/04 ,  H05K1/00

CPC classification number: H05K3/064 ,  H05K1/116 ,  H05K3/0094 ,  H05K3/061 ,  H05K3/065 ,  H05K3/108 ,  H05K3/421 ,  H05K3/427 ,  H05K2201/09381 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/098 ,  H05K2203/0517 ,  H05K2203/0577 ,  H05K2203/0582 ,  H05K2203/1184 ,  H05K2203/1394

Abstract: As means for solving a problem of a positional shift of a land and a hole which is caused by an alignment in the formation of an etching resist layer and a plated resist layer in a method of manufacturing a circuit board, there are provided a method of manufacturing a circuit board including the steps of forming a first resin layer on a surface of an insulating substrate having a conductive layer on the surface and an internal wall of a through hole or/and a non-through hole, forming a second resin layer which is insoluble or slightly soluble in a developing solution for the first resin layer on the first resin layer provided on the surface conductive layer, and removing the first resin layer provided over the hole with the developing solution for the first resin layer, and a method of manufacturing a circuit board including the step of uniformly charging a surface of the first resin layer to induce a potential difference to the first resin layer provided over the hole and the first resin layer provided on the surface conductive layer before forming the second resin layer. Moreover, there is provided a circuit board having a hole with a small positional shift and high precision.

Abstract translation: 作为在电路基板的制造方法中解决在形成抗蚀剂层和电镀抗蚀剂层时的取向引起的焊盘和孔的位置偏移的问题的方法，提供了一种方法， 制造电路板，包括以下步骤：在表面上具有导电层的绝缘基板的表面上形成第一树脂层和通孔或/或非通孔的内壁，形成第二树脂层，所述第二树脂层 在设置在表面导电层上的第一树脂层上的第一树脂层的显影液中不溶或微溶，用第一树脂层的显影液除去设在孔上的第一树脂层， 制造电路板，包括对第一树脂层的表面均匀充电以对设置在孔上的第一树脂层引起电位差的步骤， 在形成第二树脂层之前，在表面导电层上设置阴极层。 此外，提供一种电路板，其具有位置偏移小且精度高的孔。

公开(公告)号：US07470863B2

公开(公告)日：2008-12-30

申请号：US11338402

申请日：2006-01-24

Applicant: Hanyi Ding ,  Brian P. Welch

Inventor： Hanyi Ding ,  Brian P. Welch

IPC: H05K1/16

CPC classification number: H05K1/024 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/0792 ,  H05K2201/09581 ,  H01L2924/00

Abstract: A microelectronic device and method of making the microelectronic device is provided. A dielectric substrate having first and second surfaces is provided. A first component, located in the dielectric substrate between the first and second surfaces of the dielectric substrate is formed. The first component includes a first interface and a second interface. A second component located in the dielectric substrate and spaced relative to the first component is formed, and a first low permittivity material is formed having a predetermined thickness and a first and second surface, the first surface of the low permittivity material is adjacent to or in contact with a first portion of the first interface of the first component. The first low permittivity material substantially reduces capacitive parasitics of the first component, resulting in a substantially higher characteristic impedance of the first component during operation of the microelectronic device.

Abstract translation: 提供微电子器件和制造微电子器件的方法。 提供具有第一和第二表面的电介质基片。 形成位于电介质基板之间的电介质基板的第一和第二表面之间的第一部件。 第一组件包括第一接口和第二接口。 形成位于电介质基板中并相对于第一部件间隔开的第二部件，并且形成具有预定厚度的第一低介电常数材料和第一和第二表面，低介电常数材料的第一表面邻近或介于 与第一部件的第一界面的第一部分接触。 第一低介电常数材料显着地减小了第一部件的电容寄生效应，导致在微电子器件工作期间第一部件的特征阻抗基本上更高。

公开(公告)号：US20080289178A1

公开(公告)日：2008-11-27

申请号：US11753996

申请日：2007-05-25

Applicant: Michael Nashner ,  Jeff Howerton

Inventor： Michael Nashner ,  Jeff Howerton

IPC: H05K5/02 ,  H01Q1/00

CPC classification number: H05K3/445 ,  H05K1/053 ,  H05K3/4061 ,  H05K5/0247 ,  H05K2201/0179 ,  H05K2201/09581 ,  H05K2201/09827 ,  H05K2203/0315 ,  H05K2203/0323 ,  H05K2203/107 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of forming an isolated electrically conductive contact through a metal substrate by creating at least one via through the substrate. The at least one sidewall of the via is cleaned and coated with a non-conductive layer. In one example, the non-conductive layer is formed by anodizing the sidewall(s) of the via. In another example, the non-conductive layer may be formed by thin film deposition of a dielectric on the sidewall(s). An electrically conductive filler is then placed into the via. In the examples disclosed, the filler may be a conductive ink or a conductive epoxy.

Abstract translation: 通过形成至少一个通孔穿过衬底，通过金属衬底形成隔离的导电接触的方法。 通孔的至少一个侧壁被清洁并涂覆有非导电层。 在一个示例中，非导电层通过阳极氧化通孔的侧壁而形成。 在另一示例中，非导电层可以通过在侧壁上的电介质的薄膜沉积来形成。 然后将导电填料放入通孔中。 在所公开的实施例中，填料可以是导电油墨或导电环氧树脂。

公开(公告)号：US07420130B2

公开(公告)日：2008-09-02

申请号：US11812124

申请日：2007-06-15

Applicant: Keishiro Okamoto ,  Tomoyuki Abe ,  Motoaki Tani ,  Nobuyuki Hayashi

Inventor： Keishiro Okamoto ,  Tomoyuki Abe ,  Motoaki Tani ,  Nobuyuki Hayashi

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/445 ,  H05K1/056 ,  H05K3/426 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/09581 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The wiring board comprises a plate-shaped conductive core material 10 with a through-hole 12 formed in, an insulation layer 14 formed on the surface of the conductive core material 10 and on the inside wall of the through-hole 12, a resin 18 buried in the through-hole 12 with the insulation layer 14 formed in, wirings 22a, 22b formed on the upper surface and the undersurface of the conductive core material 10 with the insulation layer 14 formed on, and an wiring 22d formed in the through-hole 20 formed in the resin 18 and electrically connected to the wirings 22a, 22b.

Abstract translation: 布线板包括具有形成在其中的通孔12的板状导电芯材10，形成在导电芯材10的表面上的绝缘层14和通孔12的内壁上的树脂18 埋置在通孔12中，其中形成有绝缘层14，形成在形成有绝缘层14的导电芯材10的上表面和下表面上的布线22a，22b以及形成在其中的布线22d 通孔20形成在树脂18中并电连接到布线22a，22b。