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    CMOS-MEMS INTEGRATED DEVICE WITH SELECTIVE BOND PAD PROTECTION
    173.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE WITH SELECTIVE BOND PAD PROTECTION 有权
    具有选择性焊盘保护的CMOS-MEMS集成器件

    公开(公告)号：US20160318755A1

    公开(公告)日：2016-11-03

    申请号：US14699938

    申请日：2015-04-29

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE

    IPC: B81C1/00

    CPC classification number: B81C1/00801 ,  B81B7/0025 ,  B81B2207/07 ,  B81C2201/053 ,  B81C2203/0785

    Abstract: A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.

    Abstract translation: 公开了一种用于制备半导体晶片的方法和系统。 在第一方面，该方法包括在半导体晶片上的图案化的顶部金属上提供钝化层，蚀刻钝化层以使用第一掩模打开半导体晶片中的接合焊盘，在半导体晶片上沉积保护层，图案化 使用第二掩模的保护层，并且使用第三掩模蚀刻钝化层以打开半导体晶片中的其它电极。 该系统包括MEMS器件，其还包括第一基底和与第一基底结合的第二基底，其中第二基底是通过上述方法的步骤制备的。

    Fabrication method for a chip package
    178.
    发明授权
    Fabrication method for a chip package 有权
    芯片封装的制造方法

    公开(公告)号：US09064950B2

    公开(公告)日：2015-06-23

    申请号：US14135506

    申请日：2013-12-19

    Applicant: XINTEC INC.

    Inventor： Chia-Lun Tsai ,  Chia-Ming Cheng ,  Long-Sheng Yeou

    IPC: H01L21/78 ,  B81C1/00

    CPC classification number: H01L21/78 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00825 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0118

    Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

    Abstract translation: 本发明的实施例涉及一种芯片封装及其制造方法，其包括芯片保护层或附加的蚀刻停止层，以覆盖导电焊盘，以防止切割残留物损坏或划伤导电焊盘。 根据另一个实施例，当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时，可以使用芯片保护层，其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层， 形成随后的半导体制造工艺的开口。

    ELECTRONIC DEVICE
    179.
    发明申请
    ELECTRONIC DEVICE 审中-公开
    电子设备

    公开(公告)号：US20150076626A1

    公开(公告)日：2015-03-19

    申请号：US14210218

    申请日：2014-03-13

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Naofumi NAKAMURA

    IPC: B81C1/00 ,  H01G5/16 ,  B81B3/00

    CPC classification number: B81C1/00793 ,  B81B3/0021 ,  B81B3/0089 ,  B81B2201/0221 ,  B81B2203/0118 ,  B81B2203/053 ,  B81C1/00293 ,  B81C2201/053 ,  B81C2203/0145 ,  H01G5/16 ,  H01G5/18

    Abstract: According to one embodiment, an electronic device includes a substrate, a first electrode provided stationary above the substrate and used for a variable capacitor, a second electrode provided movable above or below the first electrode and used for the variable capacitor, a first protective insulation film provided on a first surface of the first electrode, the first surface facing the second electrode, and a second protective insulation film provided on a second surface of the second electrode, the second surface facing the first electrode.

    Abstract translation: 根据一个实施例，电子设备包括基板，设置在基板上方并用于可变电容器的第一电极，设置在第一电极上方或下方并可用于可变电容器的第二电极，第一保护绝缘膜 设置在所述第一电极的第一表面上，所述第一表面面向所述第二电极，以及设置在所述第二电极的第二表面上的第二保护绝缘膜，所述第二表面面向所述第一电极。

    MEMS STRUCTURE WITH IMPROVED SHIELDING AND METHOD
    180.
    发明申请
    MEMS STRUCTURE WITH IMPROVED SHIELDING AND METHOD 审中-公开
    具有改进的屏蔽和方法的MEMS结构

    公开(公告)号：US20140370638A1

    公开(公告)日：2014-12-18

    申请号：US14302385

    申请日：2014-06-11

    Applicant: mCube Inc.

    Inventor： TE-HSI "TERRENCE" LEE ,  Sudheer S. Sridharamurthy ,  Shingo Yoneoka ,  Wenhua Zhang

    IPC: B81C1/00

    CPC classification number: B81B7/0022 ,  B81B3/0086 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2207/11 ,  B81C1/00246 ,  B81C1/0038 ,  B81C1/00531 ,  B81C1/00801 ,  B81C2201/053

    Abstract: A method for fabricating an integrated MEMS-CMOS device. The method can include providing a substrate member having a surface region and forming a CMOS IC layer having at least one CMOS device overlying the surface region. A bottom isolation layer can be formed overlying the CMOS IC layer and a shielding layer and a top isolation layer can be formed overlying a portion of bottom isolation layer. The bottom isolation layer can include an isolation region between the top isolation layer and the shielding layer. A MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer, and can be etched to form at least one MEMS structure having at least one movable structure and at least one anchored structure.

    Abstract translation: 一种用于制造集成MEMS-CMOS器件的方法。 该方法可以包括提供具有表面区域的衬底构件，并形成具有覆盖在表面区域上的至少一个CMOS器件的CMOS IC层。 可以形成覆盖CMOS IC层的底部隔离层，并且可以形成覆盖在底部隔离层的一部分上的屏蔽层和顶部隔离层。 底部隔离层可以包括顶部隔离层和屏蔽层之间的隔离区域。 覆盖顶部隔离层，屏蔽层和底部隔离层的MEMS层，并且可被蚀刻以形成具有至少一个可移动结构和至少一个锚定结构的至少一个MEMS结构。

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