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    High frequency module
    171.
    发明授权
    High frequency module 失效
    高频模块

    公开(公告)号：US06476695B1

    公开(公告)日：2002-11-05

    申请号：US09578691

    申请日：2000-05-26

    Applicant: Masumi Nakamichi

    Inventor： Masumi Nakamichi

    IPC: H01P308

    CPC classification number: H05K1/167 ,  H05K1/0237 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2201/10045 ,  H05K2203/1461

    Abstract: A high frequency module is provided with a resistor array layer with interconnections, in which a plurality of resistor elements having a prescribed resistance value are formed as an array, and in which an interconnection pattern for providing electrical connection to each resistor element is formed in advance. Additionally, a capacitor array layer with interconnection in which a plurality of capacitor elements having a prescribed capacitance value are formed as an array and an interconnection pattern for providing electrical connection to each capacitor element is also formed in advance for later use. A desired circuit constant is obtained by providing interconnections among the plurality of resistor elements and among the plurality of capacitor elements, respectively, in any given combination by simply modifying the respective interconnection patterns instead of the entire module. With this configuration, a high frequency module of a more compact and lighter type which facilitates design modification is provided at a low cost.

    Abstract translation: 高频模块设置有具有互连的电阻器阵列层，其中具有规定电阻值的多个电阻元件形成为阵列，并且其中预先形成用于提供与每个电阻器元件的电连接的互连图案 。 此外，具有互连的电容器阵列层，其中具有规定的电容值的多个电容器元件形成为阵列，并且还预先形成用于提供与每个电容器元件的电连接的互连图案供稍后使用。 通过仅通过简单地修改相应的互连图案而不是整个模块，分别在多个电阻元件之间和多个电容器元件之间分别提供互连来获得期望的电路常数。 利用这种配置，以低成本提供了便于设计修改的更紧凑和更轻型的高频模块。

    Multi-layer circuit assembly and process for preparing the same
    172.
    发明申请
    Multi-layer circuit assembly and process for preparing the same 失效
    多层电路组装及其制备方法

    公开(公告)号：US20020125040A1

    公开(公告)日：2002-09-12

    申请号：US09901373

    申请日：2001-07-09

    Inventor： Lance C. Sturni ,  Kevin C. Olson

    IPC: H05K001/03 ,  H01K003/10

    CPC classification number: C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

    Abstract: A process for fabricating a multi-layer circuit assembly is provided comprising the following steps: (a) providing a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the electrically conductive core to form a conformal coating on all exposed surfaces of the electrically conductive core; (c) ablating the surface of the dielectric coating in a predetermined pattern to expose sections of the electrically conductive core; (d) applying a layer of metal to all surfaces to form metallized vias through the electrically conductive core; and (e) applying a resinous photosensitive layer to the metal layer. Additional processing steps such as circuitization may be included. Also provided are multi-layer circuit assemblies produced by the process of the present invention, comprising component layers having high via density and thermal coefficients of expansion that are compatible with those of semiconductor chips and rigid wiring boards which may be attached as components of the circuit assembly.

    Abstract translation: 提供一种制造多层电路组件的方法，包括以下步骤：（a）提供具有500至10,000个孔/平方英寸（75至1550个孔/平方厘米）的通孔密度的穿孔导电芯; （b）将电介质涂层施加到导电芯的所有暴露表面上，以在导电芯的所有暴露表面上形成共形涂层; （c）以预定图案烧蚀电介质涂层的表面以暴露导电芯的部分; （d）将金属层施加到所有表面以通过导电芯形成金属化通孔; 和（e）将树脂感光层施加到金属层。 可以包括诸如电路化的附加处理步骤。 还提供了通过本发明的方法制造的多层电路组件，包括具有高通孔密度和热膨胀系数的组件层，其与半导体芯片和刚性布线板的那些兼容，所述刚性布线板可以作为电路的部件 部件。

    Multi-layer circuit assembly and process for preparing the same
    173.
    发明申请
    Multi-layer circuit assembly and process for preparing the same 审中-公开
    多层电路组装及其制备方法

    公开(公告)号：US20020124398A1

    公开(公告)日：2002-09-12

    申请号：US09851904

    申请日：2001-05-09

    Inventor： Lance C. Sturni ,  Kevin C. Olson

    IPC: H05K005/00 ,  H05K005/04 ,  H05K005/06 ,  H05K003/30

    CPC classification number: C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: A process for fabricating a multi-layer circuit assembly is provided comprising the following steps: (a) providing a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating having a dielectric constant less than 4.00 onto all exposed surfaces of the electrically conductive core to form a conformal coating on all exposed surfaces of the electrically conductive core; (c) ablating the surface of the dielectric coating in a predetermined pattern to expose sections of the electrically conductive core; (d) applying a layer of metal to all surfaces to form metallized vias through the electrically conductive core; and (e) applying a resinous photosensitive layer to the metal layer. Additional processing steps such as circuitization may be included. Also provided are multi-layer circuit assemblies produced by the process of the present invention, comprising component layers having high via density and thermal coefficients of expansion that are compatible with those of semiconductor chips and rigid wiring boards which may be attached as components of the circuit assembly.

    Abstract translation: 提供一种制造多层电路组件的方法，包括以下步骤：（a）提供具有500至10,000个孔/平方英寸（75至1550个孔/平方厘米）的通孔密度的穿孔导电芯; （b）将介电常数小于4.00的介电涂层施加到导电芯的所有暴露表面上，以在导电芯的所有暴露表面上形成共形涂层; （c）以预定图案烧蚀电介质涂层的表面以暴露导电芯的部分; （d）将金属层施加到所有表面以通过导电芯形成金属化通孔; 和（e）将树脂感光层施加到金属层。 可以包括诸如电路化的附加处理步骤。 还提供了通过本发明的方法制造的多层电路组件，包括具有高通孔密度和热膨胀系数的组件层，其与半导体芯片和刚性布线板的那些兼容，所述刚性布线板可以作为电路的部件 部件。

    Multilayer circuit board having a capacitor and process for manufacturing same
    176.
    发明申请
    Multilayer circuit board having a capacitor and process for manufacturing same 有权
    具有电容器的多层电路板及其制造方法

    公开(公告)号：US20020084104A1

    公开(公告)日：2002-07-04

    申请号：US10074899

    申请日：2002-02-12

    Inventor： Masayuki Sasaki

    IPC: H05K001/03

    CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/002 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0394 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49156 ,  H01L2924/00

    Abstract: A multi-layer circuit board comprises: an insulating layer having upper and lower surfaces thereof, and wiring patterns arranged on the upper and lower surfaces of the insulating layer. A ferroelectric layer has a dielectric constant larger than that of the insulating layer and has upper and lower surfaces. The ferroelectric layer is arranged in the insulating layer in such a manner that the upper and lower surfaces of the ferroelectric layer coincide with the upper and lower surfaces of the insulating layer, respectively. A pair of electrode films are formed on the upper and lower surfaces of the ferroelectric layer, respectively, to define a capacitor incorporated in the multi-layer circuit board.

    Abstract translation: 多层电路板包括：具有上表面和下表面的绝缘层和布置在绝缘层的上表面和下表面上的布线图案。 铁电层的介电常数大于绝缘层的介电常数，并具有上表面和下表面。 铁电层以绝缘层的上表面和下表面分别与铁电层的上表面和下表面一致的方式设置在绝缘层中。 分别在铁电层的上表面和下表面上形成一对电极膜，以限定并入多层电路板中的电容器。

    Thin-film electronic component and motherboard
    177.
    发明申请
    Thin-film electronic component and motherboard 失效
    薄膜电子元器件和主板

    公开(公告)号：US20020070423A1

    公开(公告)日：2002-06-13

    申请号：US09998924

    申请日：2001-11-29

    Applicant: KYOCERA CORPORATION

    Inventor： Junya Takafuji

    IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

    CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/16 ,  H05K1/162 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/467 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09763 ,  H01L2924/00

    Abstract: An object of the invention is to provide a thin-film electronic component and a motherboard in which coupling strength of an external terminal to a supporting substrate is improved. The thin-film electronic component comprising: a supporting substrate; a lower electrode formed on part of the supporting substrate; an insulation layer formed on the lower electrode; an upper electrode formed on the insulation layer; a connection electrode which is formed on part of the supporting substrate located on a bottom surface of a through hole formed on the insulation layer, and is electrically connected to the lower electrode; and an external terminal disposed on the connection electrode within the through hole.

    Abstract translation: 本发明的目的是提供一种薄膜电子部件和母板，其中外部端子与支撑基板的耦合强度得到改善。 所述薄膜电子部件包括：支撑基板; 形成在所述支撑基板的一部分上的下电极; 形成在下电极上的绝缘层; 形成在绝缘层上的上电极; 连接电极，其形成在位于形成在所述绝缘层上的通孔的底面上的所述支撑基板的一部分上，并且电连接到所述下电极; 以及设置在通孔内的连接电极上的外部端子。

    Laser imaging of thin layer electronic circuitry material
    178.
    发明授权
    Laser imaging of thin layer electronic circuitry material 失效
    薄层电子电路材料的激光成像

    公开(公告)号：US06388230B1

    公开(公告)日：2002-05-14

    申请号：US09418207

    申请日：1999-10-13

    Applicant: Wayne E. Nacker ,  Richard W. Carpenter

    Inventor： Wayne E. Nacker ,  Richard W. Carpenter

    IPC: B23K2600

    CPC classification number: H05K1/167 ,  H01L21/4846 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/027 ,  H05K3/20 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/0338

    Abstract: To form thin film electrical components, a thin film having desired electrical properties is deposited on a substrate of dissimilar material. Thermal energy from a computer guided laser is used to remove selected portions of the thin film. In accordance with one aspect of the invention, the thin film is an electrically conducting material, such as platinum or doped platinum, and the substrate is metal foil, such as copper foil. The thermal energy from the laser ablates away portions of the thin film. In accordance with another aspect of the invention, a layer of zero valence metal is deposited on a dielectric material substrate which has a melting point or decomposition temperature substantially above that of the zero valence metal. The zero valence metal layer is patterned to form electronic circuitry components by computer guided laser which provides sufficient thermal energy to boil away selected portions of the zero valence metal layer. In one preferred embodiment, electronic circuitry is formed from a three-layer composite comprising nickel foil; a dielectric material, such as silica deposited on the foil; and a zinc layer deposited on the dielectric material. The zinc layer, having a boiling point substantially below the melting points of the dielectric material and the nickel foil, is patterned by laser-derived thermal energy.

    Abstract translation: 为了形成薄膜电气部件，具有期望的电性能的薄膜沉积在不同材料的基板上。 使用来自计算机引导激光器的热能来去除所选择的薄膜部分。 根据本发明的一个方面，薄膜是诸如铂或掺杂铂的导电材料，并且衬底是诸如铜箔的金属箔。 来自激光器的热能消除了薄膜的部分。 根据本发明的另一方面，一种零价金属层沉积在电介质材料基底上，其熔点或分解温度基本上高于零价金属的熔点或分解温度。 零价金属层被图案化以通过计算机引导激光器形成电子电路部件，该激光器提供足够的热能来去除零价金属层的选定部分。 在一个优选实施例中，电子电路由包括镍箔的三层复合材料形成; 介电材料，例如沉积在箔上的二氧化硅; 以及沉积在电介质材料上的锌层。 具有基本上低于介电材料和镍箔的熔点的沸点的锌层通过激光衍生的热能被图案化。

    Formation of thin film capacitors
    179.
    发明授权
    Formation of thin film capacitors 有权
    薄膜电容器的形成

    公开(公告)号：US06207522B1

    公开(公告)日：2001-03-27

    申请号：US09198285

    申请日：1998-11-23

    Applicant: Andrew T. Hunt ,  Tzyy Jiuan Hwang ,  Helmut G. Hornis ,  Wen-Yi Lin

    Inventor： Andrew T. Hunt ,  Tzyy Jiuan Hwang ,  Helmut G. Hornis ,  Wen-Yi Lin

    IPC: H01L2120

    CPC classification number: H05K1/162 ,  H01G4/085 ,  H05K3/388 ,  H05K3/467 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309

    Abstract: Thin layer capacitors are formed from a first flexible metal layer, a dielectric layer between about 0.03 and about 2 microns deposited thereon, and a second flexible metal layer deposited on the dielectric layer. The first flexible metal layer may either be a metal foil, such as a copper, aluminum, or nickel foil, or a metal layer deposited on a polymeric support sheet. Depositions of the layers is by or is facilitate by combustion chemical vapor deposition or controlled atmosphere chemical vapor deposition.

    Abstract translation: 薄层电容器由第一柔性金属层，沉积在其上的约0.03和约2微米之间的电介质层和沉积在电介质层上的第二柔性金属层形成。 第一柔性金属层可以是金属箔，例如铜，铝或镍箔，或者沉积在聚合物支撑片上的金属层。 通过燃烧化学气相沉积或受控气氛化学气相沉积，这些层的沉积是或通过其促进的。

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