公开(公告)号：US20070294890A1

公开(公告)日：2007-12-27

申请号：US11770581

申请日：2007-06-28

Applicant: Franz Gisin ,  Greg Schroeder

Inventor： Franz Gisin ,  Greg Schroeder

IPC: H01K3/10 ,  H03H7/38

CPC classification number: H05K1/116 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09718 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A printed circuit board with improved signal integrity for one or more differential signal pairs incorporates one or more conductive regions. In an exemplary embodiment, via structures for the differential pair that interconnect signal traces are isolated from the conductive region by an antipad area around the via structures and a conductive bridge. In alternate embodiment, an antipad area around the via structures includes a bridge between the via structures. The antipad area may comprise, by way of non-limiting example, a clipped circular aperture or a modified rectangular aperture. The bridge may, by non-limiting examples, comprise a portion of the conductive region to permit impedance tailoring of the differential pair with respect to the conductive region.

Abstract translation: 对于一个或多个差分信号对具有改进的信号完整性的印刷电路板包括一个或多个导电区域。 在示例性实施例中，将信号迹线互连的差分对的通孔结构通过通孔结构和导电桥周围的反面区域与导电区域隔离。 在替代实施例中，通孔结构周围的止血区域包括通孔结构之间的桥。 作为非限制性示例，止血区域可以包括夹紧的圆形孔或修改的矩形孔。 通过非限制性示例，桥可以包括导电区域的一部分，以允许差分对相对于导电区域的阻抗调整。

公开(公告)号：US20070293094A1

公开(公告)日：2007-12-20

申请号：US11453389

申请日：2006-06-15

Applicant: Robert A. Aekins

Inventor： Robert A. Aekins

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H01R13/6625 ,  H01R13/7195 ,  H05K1/0228 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/10189

Abstract: The present disclosure is directed to systems and methods for a multiport connector assembly, used in telecommunication systems, that is designed to reduce electrical port to port crosstalk noise. The assembly is adapted to reduce noise from adjacent ports by placing balancing isolators and capacitor radiators in noise reducing regions of a printed circuit board. The signals are radiated in properly selected areas to rebalance the noise generated from adjacent transmission ports. By rebalancing noise inherently coupled by adjacency of transmitters, the port to port near-end crosstalk and far-end crosstalk noise is substantially reduced.

Abstract translation: 本公开涉及用于电信系统中的多端口连接器组件的系统和方法，其被设计为减少电端口到端口串扰噪声。 该组件适于通过将平衡隔离器和电容器辐射器放置在印刷电路板的降噪区域中来减少相邻端口的噪声。 信号在适当选择的区域中辐射，以重新平衡从相邻传输端口产生的噪声。 通过重新平衡通过发射机邻接耦合的噪声，端口到端口串扰和远端串扰噪声显着降低。

公开(公告)号：US20070285860A1

公开(公告)日：2007-12-13

申请号：US11799705

申请日：2007-05-02

Applicant: Peter Shintani ,  Yoshihisa Tahara

Inventor： Peter Shintani ,  Yoshihisa Tahara

IPC: H02H3/20

CPC classification number: H04N9/641 ,  H02H9/046 ,  H04N5/44 ,  H05K1/0259 ,  H05K1/181 ,  H05K2201/09236

Abstract: An array of electrostatic discharge (ESD) devices conforms to the pitch defined by balanced signal lines on a printed wiring board (PWB) so that the array does not unduly affect the design impedance of the balanced lines.

公开(公告)号：US07307492B2

公开(公告)日：2007-12-11

申请号：US10306418

申请日：2002-11-27

Applicant: Alok Tripathi ,  Dennis J. Miller

Inventor： Alok Tripathi ,  Dennis J. Miller

IPC: H01P5/00 ,  H01P5/18 ,  G06F17/50

CPC classification number: H05K1/0245 ,  H05K1/023 ,  H05K1/0239 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/10022

Abstract: An apparatus that includes a first conducting strip having a narrowed width where the first conducting strip also acts as a first electrode for a first tapping capacitance. The first tapping capacitance has a second electrode that is: 1) parallel to the first conducting strip; and 2) closer to the first conducting strip than a second conducting strip. The second conducting strip is parallel to the first conducting strip and has a narrowed width where the second conducting strip also acts as a first electrode for a second tapping capacitance. The second tapping capacitance has a second electrode that is: 1) parallel to the second conducting strip; and 2) closer to the second conducting strip than the first conducting strip.

Abstract translation: 一种装置，其包括具有变窄宽度的第一导电条，其中所述第一导电条还用作用于第一分接电容的第一电极。 第一分接电容具有第二电极，第二电极是：1）平行于第一导电条; 和2）比第二导电带更靠近第一导电条。 第二导电带平行于第一导电带并且具有窄的宽度，其中第二导电带还用作第二分接电容的第一电极。 第二分接电容具有第二电极，该第二电极是：1）平行于第二导电带; 和2）比第一导电条更靠近第二导电条。

公开(公告)号：US07303113B2

公开(公告)日：2007-12-04

申请号：US10722432

申请日：2003-11-28

Applicant: Young Hoon Kwark ,  Christian Schuster

Inventor： Young Hoon Kwark ,  Christian Schuster

IPC: B23K31/00 ,  B23K31/02

CPC classification number: H01L24/46 ,  H01L23/66 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2224/43 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49174 ,  H01L2224/8502 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/1903 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0219 ,  H05K1/0243 ,  H05K2201/0792 ,  H05K2201/09236 ,  H05K2201/1028 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method (and structure) of making an electronic interconnection, includes, for a signal line to be interconnected, using a plurality of bonding wires configured to provide a controlled impedance effect.

Abstract translation: 制造电子互连的方法（和结构）包括用于要互连的信号线，使用被配置为提供受控阻抗效应的多个接合线。

公开(公告)号：US07301748B2

公开(公告)日：2007-11-27

申请号：US11169926

申请日：2005-06-30

Applicant: Anthony A. Anthony ,  William M. Anthony

Inventor： Anthony A. Anthony ,  William M. Anthony

IPC: H02H9/00

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/023 ,  H05K1/0237 ,  H05K2201/09236 ,  H05K2201/10378 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Abstract translation: 本发明涉及用于将有源电子元件（例如但不限于单个或多个）单个或多个集成电路芯片互连的插入器基板，以及可以包括安装基板，基板模块，印刷电路 板，集成电路芯片或其他包含导电能量路径的基板，其能够利用负载和通向能量源的能量。 插入器还将具有多层通用多功能通用导电屏蔽结构，其具有用于能量和EMI调节和保护的导电路径，其还包括可共同屏蔽的结构的共同共享和中心定位的导电路径或电极， 允许包含用于能量调节的电路架构的组合和通电的导电路径电极之间的平滑的能量相互作用，因为它涉及集成电路器件封装。 本发明可以用于有源电子部件和多层电路卡之间。 不提供制作插入器的方法，并且可以根据现有或将要开发的个人或专有的施工方法来改变。

公开(公告)号：US07292452B2

公开(公告)日：2007-11-06

申请号：US10864958

申请日：2004-06-10

Applicant: Kok-Siang Ng ,  King Keong Wong ,  Michael E. Ryan

Inventor： Kok-Siang Ng ,  King Keong Wong ,  Michael E. Ryan

IPC: H05K7/00

CPC classification number: H05K1/0245 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/09681 ,  H05K2201/0969 ,  Y10T29/49155

Abstract: A component having reference layer openings to contribute towards achieving a differential impedance in a circuit, is described herein.

Abstract translation: 这里描述了具有参考层开口以有助于实现电路中的差分阻抗的部件。

公开(公告)号：US07284221B2

公开(公告)日：2007-10-16

申请号：US11287951

申请日：2005-11-28

Applicant: Clifford L. Winings ,  Joseph B. Shuey

Inventor： Clifford L. Winings ,  Joseph B. Shuey

IPC: G06F17/50

CPC classification number: H05K1/114 ,  H05K1/0237 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/10189 ,  H05K2201/10734

Abstract: Methods for designing SMT connector footprints are disclosed. A circuit board may have disposed thereon an arrangement of SMT pads and corresponding vias. The arrangement of vias may differ from the arrangement of SMT pads. The arrangement of SMT pads may differ from the arrangement of contacts in a connector the footprint is designed to receive. The terminal ends of the contacts may be jogged or bent for electrical connection with the SMT pads. The SMT pads and vias may be arranged in a number of ways that increase signal contact density of the board, while limiting cross-talk and providing adequate impedance and routing space on the board. An interactive tool for designing such a footprint is disclosed.

Abstract translation: 公开了设计SMT连接器脚印的方法。 电路板可以在其上设置有SMT焊盘和对应的通孔的布置。 通孔的布置可能不同于SMT焊盘的布置。 SMT焊盘的布置可能不同于封装设计用于接收的连接器中的触点布置。 触点的端子可以被点动或弯曲以与SMT焊盘电连接。 SMT焊盘和通孔可以以增加板的信号接触密度的多种方式布置，同时限制串扰并且在板上提供足够的阻抗和布线空间。 公开了一种用于设计这种足迹的交互式工具。

公开(公告)号：US20070238224A1

公开(公告)日：2007-10-11

申请号：US11309151

申请日：2006-06-28

Applicant: Ning Liu

Inventor： Ning Liu

IPC: H01L21/00

CPC classification number: H05K1/0219 ,  H05K2201/09236 ,  H05K2201/09781

Abstract: A printed circuit board includes a signal layer, a pair of signal lines, and a plurality of conductive pads arranged on the signal layer. The conductive pads are located between the two signal lines for reducing crosstalk.

Abstract translation: 印刷电路板包括信号层，一对信号线和布置在信号层上的多个导电焊盘。 导电焊盘位于两个信号线之间，以减少串扰。

公开(公告)号：US20070230149A1

公开(公告)日：2007-10-04

申请号：US11807027

申请日：2007-05-24

Applicant: Matthew Bibee

Inventor： Matthew Bibee

IPC: H01R12/16

CPC classification number: H05K1/0219 ,  H01R12/523 ,  H01R13/6471 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/10189

Abstract: The embodiments of the present invention relate to an improved printed circuit board having additional rows of ground vias to reduce crosstalk in the board. A printed circuit board according to one embodiment of the present invention comprises a first row of vias and a second row of vias, each having a plurality of signal vias. The circuit board also comprises a plurality of rows of vias being coupled to a ground plane between the first row of signal vias and the second row of signal vias. According to one embodiment, the plurality of rows of vias being coupled to a ground plane comprise rows of vias having different sizes. Some of the vias are designed to receive a component, while others are generally smaller and designed to provide a return current path for the signal vias.

Abstract translation: 本发明的实施例涉及一种改进的印刷电路板，其具有附加的一排接地通孔，以减少电路板中的串扰。 根据本发明的一个实施例的印刷电路板包括第一行通孔和第二排通孔，每条通孔具有多个信号通路。 电路板还包括多个通孔的行，其耦合到第一行信号通孔和第二行信号通孔之间的接地平面。 根据一个实施例，耦合到接地平面的多排通孔包括具有不同尺寸的通孔列。 一些通孔被设计成接收组件，而其他通孔通常较小并被设计成为信号通路提供返回电流路径。