公开(公告)号：US5874770A

公开(公告)日：1999-02-23

申请号：US731172

申请日：1996-10-10

Applicant: Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

Inventor： Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

IPC: H05K3/46 ,  H01L21/48 ,  H01L21/822 ,  H01L21/98 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L27/04 ,  H05K1/16 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H01L23/053 ,  H01L23/02 ,  H01L23/48

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/18 ,  H01L24/82 ,  H01L25/16 ,  H01L25/50 ,  H05K1/162 ,  H05K1/167 ,  H01L2224/18 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  H05K2203/0361 ,  H05K3/388 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4644 ,  Y10T29/49165

Abstract: A method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide. If the resistor and metallization layers are applied over both surfaces of the dielectric film, passive components can be fabricated on both surfaces of the dielectric film. The dielectric film can have vias therein with the resistor and metallization layers extending through the vias. A circuit chip can be attached and coupled to the passive components by metallization patterned through vias in an additional dielectric layer.

Abstract translation: 制造柔性互连膜的方法包括在电介质膜的一个或两个表面上施加电阻层; 在所述电阻层上施加金属化层，所述电阻层包括促进所述电介质膜和所述金属化层的粘附的材料; 在所述金属化层上施加电容器电介质层; 以及在电容器电介质层上施加电容器电极层。 将电容器电极层图案化以形成第一电容器电极; 对电容器电介质层进行图案化; 图案化金属化层以形成电阻器; 并且金属化层和电阻层被图案化以形成电感器和第二电容器电极。 在一个实施例中，电介质膜包括聚酰亚胺，电阻层包括氮化钽，电容器介电层包括无定形氢化碳或氧化钽。 如果将电阻和金属化层施加在电介质膜的两个表面上，则可以在电介质膜的两个表面上制造无源元件。 电介质膜可以具有通孔，其中电阻器和金属化层延伸穿过通孔。 电路芯片可以通过在附加电介质层中通过通孔图案化的金属化而附接并耦合到无源部件。

公开(公告)号：US5745333A

公开(公告)日：1998-04-28

申请号：US342507

申请日：1994-11-21

Applicant: Jerome Albert Frankeny ,  Richard Francis Frankeny ,  Terry Frederick Hayden ,  Ronald Lann Imken ,  Janet Louise Rice

Inventor： Jerome Albert Frankeny ,  Richard Francis Frankeny ,  Terry Frederick Hayden ,  Ronald Lann Imken ,  Janet Louise Rice

IPC: H05K1/16 ,  H05K3/46 ,  H01G4/06

CPC classification number: H05K3/462 ,  H05K1/162 ,  H05K3/4641 ,  H01L2224/81385 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0307 ,  H05K3/4623 ,  Y10T29/435 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability. A multilayer composite laminar stackable circuit board structure is created using, as appropriate, layers having metallic cores and layers having capacitively configured cores. The multilayer laminar stackable circuit board provides direct vertical connection between surface mounted electronic components and the power, signal and capacitive decoupling layers of the composite board through the dendrites and joining metallurgy of the via and plug formations.

公开(公告)号：US5609773A

公开(公告)日：1997-03-11

申请号：US332134

申请日：1994-10-31

Applicant: Mitsuru Usui ,  Tetsuya Watanabe

Inventor： Mitsuru Usui ,  Tetsuya Watanabe

IPC: H01L21/48 ,  H05K1/16 ,  H05K3/06 ,  H05K3/38 ,  H05K3/46 ,  H05K3/00

CPC classification number: H01L21/4857 ,  H05K3/06 ,  H01L2924/0002 ,  H05K1/167 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2203/0361 ,  H05K2203/1184 ,  H05K3/064 ,  H05K3/388 ,  H05K3/467

Abstract: In a multilayer wiring board comprising a substrate on which two or more layers of wiring or insulation film are formed of different materials, for example, the wiring layer is processed so that the processed side faces of the board contour a stepped shape in the cross-sectional view of the board, whereby coverage of a film formed thereon can be improved. Specifically, first, insulation film 2 is formed on a substrate 1 and then, resistor film 3 and resistor electrode film 4 are continuously formed thereon to form a film of multiple structure. Mask 9 is formed thereon. Then, the layers is etched successively in the order of from the top layer and thereafter only the resistor electrode film 4 is further etched with an etching solution which selectively etches only the resistor electrode film 4 to form a stepwise patterned side face. Finally, the mask is removed and wiring electrode film 5 is formed.

Abstract translation: 在包括由不同材料形成有两层或多层布线或绝缘膜的基板的多层布线板中，例如，布线层被加工成使得板的加工侧面在横截面中呈阶梯状， 可以改善板的横截面图，从而可以改善其上形成的膜的覆盖。 具体地，首先，在基板1上形成绝缘膜2，然后在其上连续地形成电阻膜3和电阻电极膜4，以形成多个结构的膜。 面罩9形成在其上。 然后，以从顶层的顺序依次蚀刻各层，此后仅用选择性地蚀刻电阻器电极膜4的蚀刻溶液进一步蚀刻电阻电极膜4，以形成逐步图案化的侧面。 最后，除去掩模并形成布线电极膜5。

公开(公告)号：US5455064A

公开(公告)日：1995-10-03

申请号：US151409

申请日：1993-11-12

Applicant: William T. Chou ,  Michael G. Peters ,  Wen-chou V. Wang ,  Richard L. Wheeler

Inventor： William T. Chou ,  Michael G. Peters ,  Wen-chou V. Wang ,  Richard L. Wheeler

IPC: H01G4/33 ,  H01L21/822 ,  H01L23/12 ,  H01L23/50 ,  H01L23/538 ,  H01L23/64 ,  H01L27/04 ,  H05K1/11 ,  H05K1/16 ,  H05K3/46 ,  B05D5/12

CPC classification number: H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/642 ,  H05K1/162 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/3011 ,  H05K1/112 ,  H05K2201/0317 ,  H05K2201/09309 ,  H05K2203/0315

Abstract: A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed in the bottom contact layer and is electrically isolated from remaining portions of the bottom contact layers by insulating plugs. A bottom contact metalization layer is applied to the surface of the bottom contact layers and the insulating plugs. A dielectric layer is formed on the surface of the bottom contact metalization layer. A ground metalization via and a power metalization via are formed at the surface of the dielectric layer. A sequence of top contact layers are applied to the surface of the dielectric layer and a front side ground terminal and front side power terminal are formed. A back side ground terminal and a back side power terminal are formed at the back side of the base substrate.

Abstract translation: 通过形成穿过非导电基底基板的厚度的多个通孔并用导电材料填充通孔来形成薄膜旁路电容器，以形成接地通孔和电源通孔。 将背面金属化层序列施加到基底基板的背面。 底部接触层序列被施加到基底基板的前侧表面。 底接触电源端子形成在底部接触层中，并且通过绝缘插塞与底部接触层的剩余部分电隔离。 底部接触金属化层被施加到底部接触层和绝缘插头的表面。 在底部接触金属化层的表面上形成介电层。 在电介质层的表面形成有接地金属化通孔和功率金属化通孔。 顶层接触层序列被施加到电介质层的表面，形成前侧接地端子和前端电源端子。 背面接地端子和背面电源端子形成在基底基板的背面。

公开(公告)号：US5445922A

公开(公告)日：1995-08-29

申请号：US978813

申请日：1992-11-19

Applicant: Marshall Maple

Inventor： Marshall Maple

IPC: H01F17/00 ,  H01L27/01 ,  H05K1/16 ,  G03F7/26

CPC classification number: H01F17/0006 ,  H01L27/016 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0317 ,  Y10T29/49099

Abstract: a thin film printed circuit inductive element exhibiting low Q wherein a conductive spiral is deposited on an insulating substrate and resistive links are connected between adjacent turns of the spiral. Inherent resonance is thereby damped out.

Abstract translation: 表现出低Q的薄膜印刷电路感应元件，其中导电螺旋沉积在绝缘基板上，电阻链路连接在螺旋的相邻匝之间。 因此阻尼了固有共振。

公开(公告)号：US5409567A

公开(公告)日：1995-04-25

申请号：US234205

申请日：1994-04-28

Applicant: William H. Lytle ,  Kevin H. Chang ,  Peter C. East

Inventor： William H. Lytle ,  Kevin H. Chang ,  Peter C. East

IPC: C23F1/18 ,  H05K3/06 ,  H05K3/10 ,  H05K3/38 ,  B44C1/22 ,  C23F1/00

CPC classification number: C23F1/18 ,  H05K3/067 ,  H05K3/108 ,  H05K2201/0317 ,  H05K3/388

Abstract: A method for etching a composite copper layer (40) of plated copper (20) overlying physical vapor deposited copper (30) comprises etching the plated copper (20) at a rate less than the rate of etch of the physical vapor deposited copper (30). The etching may be accomplished with an aqueous solution of ammonium peroxydisulfate with molar concentrations of ammonium ions between 0.0438 and 0.1052, at a temperature between 30.degree. and 35.degree. C. and with the pH buffered to remain at a value between 1 and 1.8.

Abstract translation: 用于蚀刻覆盖物理蒸气沉积铜（30）的电镀铜（20）的复合铜层（40）的方法包括以低于物理蒸汽沉积铜（30）的蚀刻速率的速率蚀刻镀覆铜（20） ）。 蚀刻可以用摩尔浓度为0.0438和0.1052之间的铵离子的过二硫酸铵的水溶液在30℃至35℃的温度下进行，并且缓冲的pH保持在1和1.8之间。

公开(公告)号：US5308927A

公开(公告)日：1994-05-03

申请号：US77959

申请日：1993-06-18

Applicant: Norihiro Hosoi

Inventor： Norihiro Hosoi

IPC: H01L21/48 ,  H05K1/00 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K1/09

CPC classification number: H01L21/4857 ,  H05K3/105 ,  H05K3/108 ,  H05K3/24 ,  H05K1/0393 ,  H05K2201/0154 ,  H05K2201/0317 ,  H05K2201/0376 ,  H05K2201/2063 ,  H05K2203/092 ,  H05K2203/1136 ,  H05K3/064 ,  H05K3/107

Abstract: A wiring board, which can be efficiency produced and has excellent heat resistance, and a method of manufacturing the same. With ion-irradiation, a conductive layer and a metal layer are formed in an insulating substrate. In the vicinity of the interface between the insulating substrate and the metal layer, a composition region, which includes the atoms of the insulating substrate and the metal layer, is formed by applying ions to a metal layer formed in the insulating substrate.

Abstract translation: 可以有效率地制造并具有优异的耐热性的布线板及其制造方法。 通过离子照射，在绝缘基板中形成导电层和金属层。 在绝缘基板和金属层之间的界面附近，通过向形成在绝缘基板上的金属层施加离子而形成包含绝缘基板和金属层的原子的组成区域。

公开(公告)号：US5221426A

公开(公告)日：1993-06-22

申请号：US799804

申请日：1991-11-29

Applicant: Theodore G. Tessier ,  John W. Stafford ,  William F. Hoffman

Inventor： Theodore G. Tessier ,  John W. Stafford ,  William F. Hoffman

IPC: H01L21/3213 ,  H05K3/02 ,  H05K3/06 ,  H05K3/10 ,  H05K3/38 ,  H05K3/46

CPC classification number: H01L21/32131 ,  H05K3/027 ,  H05K3/108 ,  H05K2201/0154 ,  H05K2201/0317 ,  H05K2203/0508 ,  H05K2203/0597 ,  H05K3/062 ,  H05K3/388 ,  H05K3/4644 ,  Y10S438/94

Abstract: An improved laser etch-back process forms a metal feature on an area of a polymeric or other non-metallic substrate. The process comprises forming a metal layer on the area that includes a first, relatively thick section, and a second, relatively thin section. Thereafter, the metal layer is uniformly irradiated with a laser pulse, but not to vaporize metal from the thick section. Thus, the laser pulse selectively etches the thin section to remove the metal and expose the substrate, without disturbing the thick section, which forms the desired metal feature.

Abstract translation: 改进的激光蚀刻工艺在聚合物或其它非金属基底的区域上形成金属特征。 该方法包括在包括第一相对厚的部分和第二较薄的部分的区域上形成金属层。 此后，用激光脉冲均匀地照射金属层，但不从厚部分蒸发金属。 因此，激光脉冲选择性地蚀刻薄部分以去除金属并暴露衬底，而不会干扰形成所需金属特征的厚部分。

公开(公告)号：US5215866A

公开(公告)日：1993-06-01

申请号：US523066

申请日：1990-05-14

Applicant: Marshall Maple

Inventor： Marshall Maple

IPC: H01F17/00 ,  H01L27/01 ,  H05K1/16

CPC classification number: H01F17/0006 ,  H01L27/016 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0317 ,  Y10T29/49099

Abstract: A thin film printed circuit inductive element exhibiting low Q wherein a conductive spiral is deposited on an insulating substrate and resistive links are connected between adjacent turns of the spiral. Inherent resonance is thereby damped out.

Abstract translation: 表现出低Q的薄膜印刷电路电感元件，其中导电螺旋沉积在绝缘基板上，电阻链路连接在螺旋的相邻匝之间。 因此阻尼了固有共振。

公开(公告)号：US5172304A

公开(公告)日：1992-12-15

申请号：US795713

申请日：1991-11-21

Applicant: Jyuichiro Ozawa ,  Kikuo Wakino

Inventor： Jyuichiro Ozawa ,  Kikuo Wakino

IPC: H05K1/03 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K1/0373 ,  H05K1/167 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09672 ,  H05K3/4611

Abstract: A flat capacitor-containing wiring board, which can be arranged optionally in the interior of a multilayer substrate. This capacitor-containing wiring board has a dielectric substrate which is made of a mixture of dielectric powder and resin, and conductors which are provided on both major surfaces of the dielectric substrate. The conductors can be etched and shaped so as to form capacitors which use the interior of the wiring board as their dielectric layers. With this wiring board, it is possible to etch the conductors so that the values of the capacitors can be freely selected over a wide range, the wiring board is flexible to some extent, and no pinholes or defects are defined over a wide area. Preferably, the board has a greater relative resin content near its surfaces than in its interior, which improves the dielectric characteristics of the board. The increased resin content may be provided by resin adhesive layers on the surfaces which permeate the board to some extent.

Abstract translation: 一种扁平的含电容器的布线板，其可选地布置在多层基板的内部。 该含电容器的布线基板具有由电介质粉末和树脂的混合物构成的电介质基板和设置在电介质基板的两个主表面上的导体。 可以对导体进行蚀刻和成形，以形成使用布线板的内部作为其电介质层的电容器。 利用该布线板，可以蚀刻导体，使得可以在宽范围内自由选择电容器的值，布线板在一定程度上是柔性的，并且在广泛的区域上没有限定针孔或缺陷。 优选地，板在其表面附近具有比在其内部更大的相对树脂含量，这改善了板的介电特性。 增加的树脂含量可以通过在一定程度上渗透到板的表面上的树脂粘合剂层来提供。