公开(公告)号：US20080297274A1

公开(公告)日：2008-12-04

申请号：US12188271

申请日：2008-08-08

Applicant: WILLIAM J. BORLAND ,  G. Sidney Cox ,  David Ross McGregor

Inventor： WILLIAM J. BORLAND ,  G. Sidney Cox ,  David Ross McGregor

IPC: H03H7/00 ,  H01G4/00

CPC classification number: H05K1/167 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/0361 ,  H05K2203/1461 ,  Y10T29/435

Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode; a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0.

Abstract translation: 本发明涉及可以嵌入在印刷线路板的层内的电容/电阻装置。 嵌入器件节省了电路板表面的空间，并减少了焊接连接的数量，从而提高了可靠性。 更具体地，该装置包括第一金属箔; 第二金属箔; 由所述第一金属箔形成的第一电极; 设置在所述第一电极上的电介质; 形成在电介质上并与电介质相邻的电阻元件; 导电迹线 以及由所述第二金属箔形成并且设置在所述电介质上并与所述电阻元件电接触的第二电极，其中所述电介质设置在所述第一电极和所述第二电极之间，并且其中所述电介质包括介电常数小于 4.0。

公开(公告)号：US20080289861A1

公开(公告)日：2008-11-27

申请号：US11910142

申请日：2007-02-14

Applicant: Hyung Wook Lee

Inventor： Hyung Wook Lee

IPC: H05K1/00 ,  B29C65/72

CPC classification number: H05K3/361 ,  H01L2224/48091 ,  H05K1/0393 ,  H05K3/064 ,  H05K3/281 ,  H05K3/323 ,  H05K3/4611 ,  H05K3/4635 ,  H05K3/4691 ,  H05K3/4694 ,  H05K2201/0191 ,  H05K2201/0355 ,  H05K2201/043 ,  H05K2201/09127 ,  H05K2201/09972 ,  H01L2924/00014

Abstract: Disclosed are a multi-layer flexible printed circuit board and a method for manufacturing the same. The multi-layer flexible printed circuit board includes an adhesion sheet from which a pressing and heating area is cut, an upper base layer, from which the pressing and heating area is cut, on the adhesion sheet, and a lower base layer under to the adhesion sheet.

Abstract translation: 公开了一种多层柔性印刷电路板及其制造方法。 多层柔性印刷电路板包括：加压区域被切割的粘合片，粘合片上的加压区域被切割的上基层和下基层 粘合片。

公开(公告)号：US07453702B2

公开(公告)日：2008-11-18

申请号：US11253734

申请日：2005-10-20

Applicant: Kiyotaka Tsukada ,  Toshimasa Iwata ,  Terumasa Ninomaru ,  Takamichi Sugiura

Inventor： Kiyotaka Tsukada ,  Toshimasa Iwata ,  Terumasa Ninomaru ,  Takamichi Sugiura

IPC: H05K1/18 ,  H05K1/16

CPC classification number: H05K1/167 ,  H05K3/108 ,  H05K3/382 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2203/0338 ,  H05K2203/0384

Abstract: A printed wiring board comprises the insulating layer 11 (12); at least one resistance element 311 (312) comprising a metal as a main component has 0.5 to 5 μm of a roughened surface in an arithmetic means height in the one surface, in −Z direction, and 5% to 50% of the arithmetic mean height in average thickness, which is embedded close to a surface on one side of the insulating layer 11 and a conductive pattern wired surface is composed of the one surface of the resistance element and the one side of the insulating layer 11; and the conductive pattern 351 (352), arranged on the conductive pattern wired surface, is connected to the terminal of the resistance element 311 (312). With this structure, it is provided the printed wiring board comprising the resistance element having an accurate and stable resistance value in a broader resistance value range.

Abstract translation: 印刷电路板包括绝缘层11（12）; 包含金属作为主要成分的至少一个电阻元件31 1（31 2 2）在一个表面的算术装置高度上具有0.5-5μm的粗糙表面 在-Z方向上，并且平均厚度的算术平均高度的5％至50％嵌入在绝缘层11的一侧上的表面附近，并且导电图案布线表面由 电阻元件和绝缘层11的一侧; 并且布置在导电图案布线表面上的导电图案35 1（35 2 2）连接到电阻元件31的端子1 （31＆lt; 2＆gt;）。 利用这种结构，提供了包括电阻元件在宽电阻值范围内具有精确且稳定的电阻值的印刷电路板。

公开(公告)号：US20080268266A1

公开(公告)日：2008-10-30

申请号：US11792230

申请日：2005-12-01

Applicant: Koji Hirota ,  Naoki Nakazawa

Inventor： Koji Hirota ,  Naoki Nakazawa

IPC: B32B15/08

CPC classification number: G11B5/4833 ,  B32B15/08 ,  B32B15/18 ,  B32B15/20 ,  B32B27/20 ,  C08G73/1042 ,  C08G73/1067 ,  H05K1/0346 ,  H05K1/056 ,  H05K2201/0154 ,  H05K2201/0355 ,  Y10T428/31681

Abstract: A polyimide metal laminate including a polyimide resin having a copper foil and a stainless steel foil formed on respective sides of the polyimide resin, or a polyimide resin having two stainless steel foils formed on both sides of the polyimide resin, the polyimide metal laminate having: a peel strength of 1.0 kN/m or more between the polyimide resin and the stainless steel foil or copper foil; a peel strength of 1.0 kN/m or more between the polyimide resin and the stainless steel foil or copper foil after the polyimide metal laminate has been subjected to a heat treatment at 350° C. for 60 minutes; and no expansion or deformation after the polyimide metal laminate has been subjected to the heat treatment at 350° C. for 60 minutes.

Abstract translation: 在聚酰亚胺树脂的两侧形成有具有铜箔的聚酰亚胺树脂和不锈钢箔的聚酰亚胺金属层叠体，或者在聚酰亚胺树脂的两面形成有两根不锈钢箔的聚酰亚胺树脂， 聚酰亚胺树脂与不锈钢箔或铜箔之间的剥离强度为1.0kN / m以上; 在聚酰亚胺金属层压体在350℃下进行热处理60分钟后，聚酰亚胺树脂与不锈钢箔或铜箔之间的剥离强度为1.0kN / m以上。 并且在聚酰亚胺金属层压体在350℃下经受热处理60分钟后没有膨胀或变形。

公开(公告)号：US07435675B2

公开(公告)日：2008-10-14

申请号：US11479400

申请日：2006-06-30

Applicant: Huankiat Seh ,  Yongki Min

Inventor： Huankiat Seh ,  Yongki Min

IPC: H01L21/4763

CPC classification number: H05K1/162 ,  H05K1/112 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09763 ,  H05K2203/0113 ,  H05K2203/0353 ,  H05K2203/061

Abstract: A method of forming a pre-patterned high-k dielectric film onto a support layer. The method includes: providing a support layer; providing a template defining template openings therein exhibiting a pattern that is a mirror image of a pattern of the pre-patterned high-k dielectric film; disposing the template onto the support layer; providing a high-k precursor material inside the template openings; curing the high-k precursor material inside the template openings to yield a cured film; and removing the template from the support layer after curing to leave the cured film on the conductive film.

Abstract translation: 将预图案化的高k电介质膜形成在支撑层上的方法。 该方法包括：提供支撑层; 提供其中示出模板开口的模板，其中显示作为预图案化高k电介质膜的图案的镜像的图案; 将模板设置在支撑层上; 在模板开口内提供高k前体材料; 固化模板开口内的高k前体材料以产生固化膜; 并且在固化之后从支撑层去除模板以将固化膜留在导电膜上。

公开(公告)号：US20080210457A1

公开(公告)日：2008-09-04

申请号：US12000575

申请日：2007-12-13

Applicant: Hiroaki Hiratsuka ,  Hiroshi Ishikawa ,  Masaaki Tsutsumida

Inventor： Hiroaki Hiratsuka ,  Hiroshi Ishikawa ,  Masaaki Tsutsumida

IPC: H05K1/03 ,  H05K3/06

CPC classification number: H05K3/328 ,  H01L23/4985 ,  H01L24/50 ,  H01L24/86 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/351 ,  H05K1/0393 ,  H05K3/4084 ,  H05K3/4092 ,  H05K2201/0355 ,  H05K2201/0382 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/10681 ,  H05K2203/063 ,  Y10T29/49156 ,  H01L2924/00

Abstract: A tape carrier for semiconductor device has a resin tape provided with an opening section for bonding, and a wiring lead formed on the resin tape. The wiring lead has a notched section disposed in the opening section and including a notch width WN, and a lead width WL at a position where a bonding tool contacts the wiring lead, and a ratio of the notch width WN to the lead width WL is more than 0.5 and less than 0.685. A method for making the tape carrier includes laminating the metal foil on one surface of the resin tape including the opening section for bonding, and forming the wiring lead in the metal foil by photolithography such that the wiring lead has the notched section disposed in the opening section and including the notch width WN, and the lead width WL at the position where the bonding tool contacts the wiring lead.

Abstract translation: 用于半导体器件的带载体具有设置有用于接合的开口部分的树脂带和形成在树脂带上的布线引线。 布线引线具有设置在开口部分中并且在接合工具接触布线的位置处具有切口宽度W N N和引线宽度W L L的切口部分 引线，并且切口宽度W N N与引线宽度W L的比率大于0.5且小于0.685。 制造带载体的方法包括将金属箔层压在包括用于接合的开口部分的树脂带的一个表面上，并且通过光刻法在金属箔中形成布线引线，使得布线引线具有设置在开口中的切口部分 并且包括切口宽度W N N和在接合工具与布线引线接触的位置处的引线宽度W L L。

公开(公告)号：US20080185178A1

公开(公告)日：2008-08-07

申请号：US12011725

申请日：2008-01-29

Applicant: Rikiya Okimoto ,  Yoji Ueda ,  Satoru Tomekawa ,  Tousaku Nishiyama ,  Shozo Ochi

Inventor： Rikiya Okimoto ,  Yoji Ueda ,  Satoru Tomekawa ,  Tousaku Nishiyama ,  Shozo Ochi

IPC: H05K1/11

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/113 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/10674 ,  H05K2203/0191 ,  H05K2203/1461 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A circuit board of the present invention, includes: an electrical insulating layer including at least one layer of electrical insulating base; and a conductive portion formed in a via hole provided in the electrical insulating base. A land for mounting only is disposed on at least one surface of the electrical insulating base that is arranged at an outermost layer. According to a method for manufacturing a circuit board of the present invention, includes the steps of: forming a via hole in an electrical insulating base; filling the via hole with a conductive paste; laminating a metal foil or a releasing sheet on the electrical insulating base, and placing a jig for pressing above and below the lamination, followed by hot-pressing so as to apply heat and pressure thereto, so as to form a conductive portion made of the conductive paste in the via hole; and forming a land for mounting only on at least one surface of the electrical insulating base that is arranged at an outermost layer. Thereby, a circuit board can be provided, having a land for mounting formed with a narrow pitch.

Abstract translation: 本发明的电路板包括：电绝缘层，其包括至少一层电绝缘基底; 以及形成在设置在电绝缘基底中的通孔中的导电部分。 仅用于安装的地面设置在布置在最外层的电绝缘基底的至少一个表面上。 根据本发明的电路基板的制造方法，其特征在于，包括以下步骤：在电绝缘基体中形成通孔; 用导电膏填充通孔; 在电绝缘基底上层叠金属箔或脱模片，并且在层压体的上下配置压入夹具，然后进行热压，以对其进行加热和加压，从而形成由 导电膏在通孔中; 并且形成用于仅安装在布置在最外层的电绝缘基底的至少一个表面上的平台。 由此，可以提供具有窄间距形成的用于安装的台面的电路板。

公开(公告)号：US20080174016A1

公开(公告)日：2008-07-24

申请号：US11965404

申请日：2007-12-27

Applicant: Tetsuro Sato ,  Makoto Yamagata ,  Noriaki Iwata

Inventor： Tetsuro Sato ,  Makoto Yamagata ,  Noriaki Iwata

IPC: H01L23/48 ,  B32B3/00

CPC classification number: H05K1/0346 ,  H01L2924/0002 ,  H05K2201/0154 ,  H05K2201/0355 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A flexible printed wiring board is characterized by a laminate formed by directly laminating an electrodeposited copper foil having S side and M side, each of S side and M side having a different surface roughness, the surface roughness (Rzjis) of the deposition plain side being 1.0 μm or less, and the glossiness of the M side [Gs(60°)] being 400 or more, on a surface of an insulating layer being a substrate layer made of a resin having both of an imide structure and an amide structure in the molecule; and forming a wiring pattern by etching the electrodeposited copper foil. By using a resin having both of an imide structure and an amide structure in the molecule as the insulating layer, a flexible printed wiring board having excellent properties such as mechanical properties, heat resistance, alkali resistance and the like, especially a COF substrate is provided.

Abstract translation: 柔性印刷电路板的特征在于，通过直接层叠具有S侧和M侧的电解铜箔，S面和M侧的每一面具有不同的表面粗糙度，沉积平面的表面粗糙度（Rzjis）为 1.0μm或更小，并且在作为由具有酰亚胺结构和酰胺结构的树脂制成的基材层的绝缘层的表面上，M侧[Gs（60°）]的光泽度为400以上 分子; 以及通过蚀刻所述电沉积铜箔形成布线图案。 通过在分子中使用具有酰亚胺结构和酰胺结构的树脂作为绝缘层，提供了具有优异性能如机械性能，耐热性，耐碱性等的柔性印刷线路板，特别是COF基材 。

公开(公告)号：US20080166502A1

公开(公告)日：2008-07-10

申请号：US12007386

申请日：2008-01-09

Applicant: Kazuo Nakamae

Inventor： Kazuo Nakamae

IPC: C23C14/04

CPC classification number: C23C26/00 ,  H05K3/046 ,  H05K2201/0108 ,  H05K2201/0355 ,  H05K2203/0528 ,  H05K2203/107

Abstract: The present invention relates to a metal film pattern forming method by which a metal film pattern can be formed easily on a substrate. In the method, a metal film is caused to adhere to the surface of a substrate comprised of an insulating material having heat resistant properties. By illuminating a laser beam on the metal film on the substrate directly or via a glass plate, abrasion is caused on a portion of the metal film that is illuminated with the laser beam. A substrate having a metal film pattern adhered to the surface thereof is obtained through the abrasion by separating the metal film from the substrate surface after the illumination of the laser.

Abstract translation: 金属膜图案形成方法技术领域本发明涉及能够容易地在基板上形成金属膜图案的金属膜图案形成方法。 在该方法中，使金属膜附着在由具有耐热性的绝缘材料构成的基板的表面上。 通过直接或通过玻璃板在基板上的金属膜上照射激光束，在用激光束照射的金属膜的一部分上产生磨损。 通过在激光照射之后将金属膜与基板表面分离，通过磨损获得附着在其表面上的金属膜图案的基板。

公开(公告)号：US07393720B2

公开(公告)日：2008-07-01

申请号：US10905931

申请日：2005-01-27

Applicant: Shao-Chien Lee ,  Tzyy Jang Tseng ,  Chang-Ming Lee

Inventor： Shao-Chien Lee ,  Tzyy Jang Tseng ,  Chang-Ming Lee

IPC: H01L21/31

CPC classification number: H05K3/4038 ,  H05K3/423 ,  H05K3/4644 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2203/0369 ,  H05K2203/0733 ,  H05K2203/1476

Abstract: A method for fabricating an electrical interconnect structure is adapted for a circuit board manufacturing process. The circuit board comprises a conductive substrate, which comprises a first conductive layer and a bump conductive layer. The bump conductive layer is patterned to form at least one bump over the first conductive layer. Then, a dielectric layer is formed over the first conductive layer and the bump. A second conductive layer is formed over the dielectric layer. At least one blind hole is formed in the second conductive layer and the dielectric layer, passing through the second conductive layer and the dielectric layer to expose the top surface of the bump. A conductive material is filled in the blind hole, and the conductive material in the blind hole and the bump constitute a conductive post.

Abstract translation: 一种用于制造电互连结构的方法适用于电路板制造工艺。 电路板包括导电衬底，其包括第一导电层和凸块导电层。 凸块导电层被图案化以在第一导电层上形成至少一个凸块。 然后，在第一导电层和凸块之上形成电介质层。 在电介质层上形成第二导电层。 在第二导电层和电介质层中形成至少一个盲孔，穿过第二导电层和电介质层以露出凸块的顶表面。 导电材料填充在盲孔中，盲孔中的导电材料和凸块构成导电柱。