公开(公告)号：US07479039B2

公开(公告)日：2009-01-20

申请号：US11846733

申请日：2007-08-29

Applicant: Jim Chin-Nan Ni ,  Abraham C. Ma ,  Paul Hsueh ,  Ming-Shiang Shen

Inventor： Jim Chin-Nan Ni ,  Abraham C. Ma ,  Paul Hsueh ,  Ming-Shiang Shen

IPC: H01R13/66

CPC classification number: G06K19/07743 ,  A45C2011/188 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G06K19/077 ,  G06K19/07732 ,  G07C9/00087 ,  H05K1/117 ,  H05K1/118 ,  H05K1/189 ,  H05K3/284 ,  H05K3/4691 ,  H05K2201/091 ,  H05K2201/10159 ,  H05K2203/1527

Abstract: A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an external Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Dividers between openings in the upper case that expose the SD contact pads also support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline. A metal switch-bar or an over-molded controller die may be substituted.

Abstract translation: 闪存设备具有印刷电路板组件（PCBA），PCB组件具有闪存芯片和控制器芯片。 控制器芯片包括一个外部安全数字（SD）接口，以及一个处理单元，用于从闪存芯片中读取数据块。 PCBA被封装在上壳体和下壳体内，PCB上的SD接触垫通过上壳体中的接触开口配合。 暴露SD接触垫的上壳体中的开口之间的分隔线也以与设备中心线倾斜的角度支撑PCB。 PCB在远端向上倾斜，以允许安装在PCB底部表面的芯片的厚度更大，并且在插入端向下倾斜以将SD接触垫定位在中心线附近。 金属开关杆或过模制的控制器管芯可以被替代。

公开(公告)号：US07470342B2

公开(公告)日：2008-12-30

申请号：US11037252

申请日：2005-01-19

Applicant: Atsushi Ito ,  Masaaki Deguchi ,  Hisaki Sakurai

Inventor： Atsushi Ito ,  Masaaki Deguchi ,  Hisaki Sakurai

IPC: B32B15/00

CPC classification number: B41J2/1632 ,  B41J2/1609 ,  B41J2/1623 ,  B41J2/1626 ,  B41J2002/14217 ,  B41J2002/14225 ,  B41J2002/14362 ,  H05K3/4638 ,  H05K2201/091 ,  H05K2203/167 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49401 ,  Y10T29/49895 ,  Y10T156/1026 ,  Y10T156/1056 ,  Y10T156/1064 ,  Y10T156/108 ,  Y10T156/1304

Abstract: Plates having a predetermined pattern are provided in each frame, side by side, at certain intervals along the longitudinal direction of the frame. A plurality of positioning holes, into which pins are inserted, are formed in each frame. A retainer portion is provided so as to extend from the inner periphery of each positioning hole and is plastically deformed when a pin is inserted thereinto. By inserting a pin into each positioning hole while a plurality of frames are stacked, the outer periphery of the pin contacts the retainer portion of each positioning hole. The retainer portion is deformed to correct misalignment among a plurality of plates.

Abstract translation: 沿着框架的纵向以一定间隔并排设置在每个框架中，具有预定图案的板。 在每个框架中形成有多个插入销的定位孔。 保持部设置成从每个定位孔的内周延伸，并且当销插入其中时塑性变形。 通过在堆叠多个框架的同时将销插入每个定位孔中，销的外周与每个定位孔的保持器部分相接触。 保持器部分变形以校正多个板之间的未对准。

公开(公告)号：US20080242126A1

公开(公告)日：2008-10-02

申请号：US11877598

申请日：2007-10-23

Applicant: FU-YEN TSENG ,  CHUN-FANG CHENG ,  SSU-HAN HUANG

Inventor： FU-YEN TSENG ,  CHUN-FANG CHENG ,  SSU-HAN HUANG

IPC: H01R12/14

CPC classification number: H05K9/0039 ,  H05K1/0215 ,  H05K1/118 ,  H05K1/189 ,  H05K2201/09081 ,  H05K2201/091

Abstract: A circuit board assembly includes a circuit board, at least a conductive contact and a metal shielding device. The conductive contact is extended from a lateral edge of the circuit board and is electrically connected to the circuit board. The circuit board and the conductive contact are received in the metal shielding device with the conductive contact electrically connected to the metal shielding device. The conductive contact tightly contacts with the metal shielding device by the elasticity of the conductive contact, and the circuit board assembly can remove a static using the metal shielding device and avoid the contact failure. In addition, the conductive contact can be manufactured in manufacturing of the circuit board, the man-hour and human for affixing the conduct foam is leave out and cost is decreased.

Abstract translation: 电路板组件包括电路板，至少导电接触件和金属屏蔽装置。 导电触点从电路板的侧边缘延伸并且电连接到电路板。 电路板和导电接触件被容纳在金属屏蔽装置中，导电触头电连接到金属屏蔽装置。 导电触点通过导电触点的弹性与金属屏蔽装置紧密接触，并且电路板组件可以使用金属屏蔽装置去除静电，并避免接触故障。 此外，导电接触可以在电路板的制造中制造，用于固定导电泡沫的工时和人员被排除并且成本降低。

公开(公告)号：US07417196B2

公开(公告)日：2008-08-26

申请号：US11684147

申请日：2007-03-09

Applicant: Ryuichiro Wada ,  Tetsuya Ikeda

Inventor： Ryuichiro Wada ,  Tetsuya Ikeda

IPC: H05K1/16

CPC classification number: H05K1/186 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/023 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/183 ,  H05K3/4614 ,  H05K3/4629 ,  H05K2201/0379 ,  H05K2201/091 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A chip-type electronic component built-in multilayer board includes a multilayer board including two or more layered dielectric layers and an inner conductor pattern, and a chip-type electronic component which is provided at the interface of the upper and lower dielectric layers and includes an external terminal electrode. The external terminal electrode is connected to an in-plane conductor provided at a interface via a first connection conductor extending along the chip-type electronic component in the lower direction from the interface of the upper and lower dielectric layers, and a second connection conductor extending along the chip-type electronic component in the upper direction from the interface of the upper and lower dielectric layers.

Abstract translation: 芯片型电子元件内置多层板包括：多层基板，包括两层或多层叠层电介质层和内导体图案;以及芯片型电子元件，其设置在上下电介质层的界面处，并包括 外部端子电极。 外部端子电极通过第一连接导体连接到设置在界面处的面内导体，所述第一连接导体沿着所述芯片型电子部件从所述上部和下部电介质层的界面向下方延伸;以及第二连接导体， 沿着芯片型电子部件从上下电介质层的界面向上方延伸。

公开(公告)号：US07390692B2

公开(公告)日：2008-06-24

申请号：US11497169

申请日：2006-08-01

Applicant: Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Shingo Komatsu ,  Yoshiyuki Yamamoto ,  Seiichi Nakatani

Inventor： Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Shingo Komatsu ,  Yoshiyuki Yamamoto ,  Seiichi Nakatani

IPC: H01L21/00

CPC classification number: H05K3/328 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/94 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01039 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/0373 ,  H05K3/20 ,  H05K3/326 ,  H05K3/4614 ,  H05K3/4626 ,  H05K2201/091 ,  H05K2201/10674 ,  H01L2224/97 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/05147

Abstract: A semiconductor device (1) of the present invention includes a semiconductor element (103) including electrode parts (104), and a wiring substrate (108) including an insulation layer (101), electrode-part-connection electrodes (102) provided in the insulation layer (101), and external electrodes (107) that is provided in the insulation layer (101) and that is connected electrically with the electrode-part-connection electrodes (102), in which the electrode parts (104) and the electrode-part-connection electrodes (102) are connected electrically with each other. The insulation layer (101) has an elastic modulus measured according to JIS K6911 of not less than 0.1 GP a and not more than 5 GPa, and the electrodes (104) and the electrode-part-connection electrodes (102) are connected by metal joint.

Abstract translation: 本发明的半导体器件（1）包括包括电极部分（104）的半导体元件（103）和包括绝缘层（101）的布线基板（108），电极部分连接电极（102） 绝缘层（101）和设置在绝缘层（101）中并与电极部分连接电极（102）电连接的外部电极（107），其中电极部分（104）和 电极部分连接电极（102）彼此电连接。 绝缘层（101）具有根据JIS K6911测定的弹性模量为0.1GPa以上且5GPa以下，电极（104）和电极部连接用电极（102）通过金属 联合。

公开(公告)号：US20080136013A1

公开(公告)日：2008-06-12

申请号：US11902675

申请日：2007-09-25

Applicant: Hiroki Kamiya ,  Motoki Shimizu ,  Satoshi Takeuchi

Inventor： Hiroki Kamiya ,  Motoki Shimizu ,  Satoshi Takeuchi

IPC: H01L23/12 ,  H05K3/36

CPC classification number: H05K1/186 ,  H05K1/183 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/091 ,  H05K2201/09781 ,  H05K2201/09909 ,  H05K2201/1059 ,  H05K2201/10636 ,  H05K2201/2036 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A multilayer substrate includes an insulating base member having a plurality of resin films, an electric element embedded in the insulating base member, and a spacer. The resin films are made of a thermoplastic resin and stacked and attached to each other. At least one resin film has a through hole for inserting the electric element. The one resin film further has a plurality of protruding members. One protruding member opposes to another one protruding member so that the one and the another one contact and sandwich the electric element. The spacer is arranged between the one resin film and an adjacent resin film and is disposed at a base portion of one of the protruding members.

Abstract translation: 多层基板包括具有多个树脂膜的绝缘基底构件，嵌入绝缘基底构件中的电气元件和间隔件。 树脂膜由热塑性树脂制成并且彼此堆叠并附接。 至少一个树脂膜具有用于插入电气元件的通孔。 一个树脂膜还具有多个突出部件。 一个突出构件与另一个突出构件相对，使得一个和另一个突出构件接触并夹着电气元件。 间隔件布置在一个树脂膜和相邻的树脂膜之间，并且设置在一个突出构件的基部。

公开(公告)号：US07350297B2

公开(公告)日：2008-04-01

申请号：US11356215

申请日：2006-02-17

Applicant: Naoko Yamaguchi ,  Hideo Aoki

Inventor： Naoko Yamaguchi ,  Hideo Aoki

IPC: H01K3/10

CPC classification number: H05K3/422 ,  H05K3/1266 ,  H05K3/182 ,  H05K3/4084 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2203/0221 ,  H05K2203/0517 ,  H05K2203/0709 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T428/24917

Abstract: A first plating foundation layer is formed by printing on a front face of a sheet-shaped insulating substrate. By inserting a punch into the sheet-shaped insulating substrate having the first plating foundation layer, a through hole is formed while leaving a piece having the plating foundation layer in the portion where the punch is inserted. A second plating foundation layer is formed by printing on a rear face of the sheet-shaped insulating substrate. A first and second wiring layers composed of a metal plating layer are formed by performing electroless plating, and at the same time, a metal plating layer connecting between the first and second wiring layers is formed in the through hole using the plating foundation layer on the piece.

Abstract translation: 通过在片状绝缘基板的正面上印刷形成第一电镀基础层。 通过在具有第一电镀基础层的片状绝缘基板上插入冲头，在将冲压件插入部分留下具有电镀基础层的部件的同时形成通孔。 通过在片状绝缘基板的背面上印刷形成第二电镀基础层。 通过进行无电解电镀形成由金属镀层构成的第一和第二配线层，同时，在通孔中形成连接在第一和第二布线层之间的金属镀层，使用电镀基底层 片。

公开(公告)号：US07310869B2

公开(公告)日：2007-12-25

申请号：US11167288

申请日：2005-06-28

Applicant: Koji Nakayama

Inventor： Koji Nakayama

IPC: H01S4/00

CPC classification number: H01R12/62 ,  B41J2/14209 ,  B41J2/1609 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1634 ,  B41J2002/14217 ,  B41J2002/14225 ,  B41J2002/14306 ,  B41J2002/14459 ,  B41J2002/14491 ,  H05K1/0393 ,  H05K3/363 ,  H05K3/4007 ,  H05K2201/0191 ,  H05K2201/091 ,  H05K2203/0195 ,  Y10T29/49002 ,  Y10T29/49021 ,  Y10T29/49147 ,  Y10T29/49151

Abstract: The ink jet head is provided with a piezo-electric sheet having a plurality of contacts distributed on a surface thereof. A flat connector is fixed so as to cover the surface of the piezo-electric sheet. A plurality of conductive spots and a plurality of conductive lines are formed on a surface of the flat connector. One of each of the conductive lines is connected with one of each of the conductive spots, and the plurality of conductive spots is disposed with the same distributive pattern as the plurality of contacts. The flat connector is provided with a sheet formed of an insulating material, and is provided with a plurality of projections corresponding to the conductive spots. At least a distal end of each of the projections is covered with one of the conductive spots. The flat connector and the piezoelectric sheet are fixed such that the conductive spots make contact with the contacts of the piezo-electric sheet. Portions of the flat connector having projections are thinner than the surrounding area of the flat connector.

Abstract translation: 喷墨头设置有在其表面上分布有多个触点的压电片。 固定平面连接器以覆盖压电片的表面。 在扁平连接器的表面上形成多个导电点和多条导线。 每个导电线中的一个与每个导电点中的一个连接，并且多个导电点以与多个触点相同的分布图案设置。 扁平连接器设置有由绝缘材料形成的片材，并且设置有与导电点对应的多个突起。 每个突起的至少远端用一个导电点覆盖。 扁平连接器和压电片被固定成导电点与压电片的触点接触。 具有突起的扁平连接器的部分比扁平连接器的周围区域薄。

公开(公告)号：US07304382B2

公开(公告)日：2007-12-04

申请号：US11436957

申请日：2006-05-18

Applicant: James Douglas Wehrly, Jr. ,  Ron Orris ,  Leland Szewerenko ,  Tim Roy ,  Julian Partridge ,  David L. Roper

Inventor： James Douglas Wehrly, Jr. ,  Ron Orris ,  Leland Szewerenko ,  Tim Roy ,  Julian Partridge ,  David L. Roper

IPC: H01L23/34

CPC classification number: H01L23/13 ,  H01L23/5385 ,  H01L23/5387 ,  H01L25/18 ,  H01L2224/49175 ,  H01L2924/15311 ,  H05K1/147 ,  H05K1/182 ,  H05K1/189 ,  H05K3/326 ,  H05K2201/056 ,  H05K2201/091 ,  H05K2201/10515 ,  H05K2201/10689

Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

公开(公告)号：US20070204954A1

公开(公告)日：2007-09-06

申请号：US11747588

申请日：2007-05-11

Applicant: Frank Brunnecker ,  Alexander Hofmann

Inventor： Frank Brunnecker ,  Alexander Hofmann

IPC: B32B37/00

CPC classification number: B29C66/8322 ,  B29C65/1435 ,  B29C65/1467 ,  B29C65/1616 ,  B29C65/1635 ,  B29C65/1667 ,  B29C65/606 ,  B29C65/7841 ,  B29C66/542 ,  B29C66/7392 ,  B29C66/73921 ,  B29C66/81267 ,  B29C66/81423 ,  B29C66/843 ,  B29C2035/0822 ,  B29K2995/0027 ,  B29L2031/3061 ,  B29L2031/3425 ,  B29L2031/3481 ,  H05K3/0064 ,  H05K7/142 ,  H05K2201/0129 ,  H05K2201/091 ,  H05K2201/10598 ,  H05K2203/107

Abstract: A process is described for form locking joining of two components through plastic deformation of one of the two components. In order for the tool for forming the form locking connection not to get in direct contact with the plasticized area of the joining partners, a third component between the tool and the two components to be joined through form locking is being used, which simultaneously enters into an adhesive bond with one of the two components to be joined through form locking. The thermal energy for creating the plastic state of one of the joining partners and for developing the adhesive bond is applied through electromagnetic radiation through the third component.