公开(公告)号：US20120312590A1

公开(公告)日：2012-12-13

申请号：US13490850

申请日：2012-06-07

Applicant: Shinnosuke MAEDA ,  Hajime SAIKI ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Hajime SAIKI ,  Satoshi HIRANO

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/4007 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/544 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K1/0269 ,  H05K1/113 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09781 ,  H05K2203/072 ,  H05K2203/1105 ,  Y10T29/49155

Abstract: Disclosed is a method of manufacturing a multilayer wiring substrate having a principal plane of the substrate and a rear plane thereof, having a structure such that a plurality of resin insulating layers and a plurality of conductor layers are laminated, and a plurality of chip component connecting terminals to which chip components are connectable are disposed on the principal plane of the substrate. This method has a feature including a plating layer forming process in which product plating layers which provide the plurality of chip component connecting terminals and a dummy plating layer on the surrounding of the product plating layers are formed on the surface of an exposed outermost resin insulating layer at the principal plane of the substrate. This method permits a thickness dispersion of the chip component connecting terminals to be suppressed and permits a connection reliability thereof to the chip components to be increased.

Abstract translation: 公开了一种多层布线基板的制造方法，该多层布线基板具有基板的主面及其背面，具有层叠多个树脂绝缘层和多个导体层的结构，并且多个芯片部件连接 芯片部件可连接的端子设置在基板的主平面上。 该方法具有包括镀层形成工艺的特征，其中在露出的最外层树脂绝缘层的表面上形成了在产品镀层周围形成有多个芯片部件连接端子和虚拟镀层的产品镀层 在基板的主平面上。 该方法能够抑制芯片部件连接端子的厚度分散，并且能够提高芯片部件的连接可靠性。

公开(公告)号：US08309861B2

公开(公告)日：2012-11-13

申请号：US12705776

申请日：2010-02-15

Applicant: Toshiya Asano ,  Shinnosuke Maeda

Inventor： Toshiya Asano ,  Shinnosuke Maeda

IPC: H05K1/16

Abstract: A wiring board assembly includes a rectangular plate-shaped wiring board having a plurality of resin insulation layers and conduction layers alternately laminated together to define opposite first and second main surfaces and a plurality of connection terminals arranged on the first main surface for surface contact with terminals of a chip and a rectangular frame-shaped reinforcing member fixed to the first main surface of the wiring board with the connection terminals exposed through an opening of the reinforcing member. The reinforcing member has a plurality of structural pieces separated by slits extending from an inner circumferential surface to an outer circumferential surface of the reinforcing member.

公开(公告)号：US20120145666A1

公开(公告)日：2012-06-14

申请号：US13312534

申请日：2011-12-06

Applicant: Shinnosuke MAEDA

Inventor： Shinnosuke MAEDA

IPC: H05K3/06

CPC classification number: H05K3/4682 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/205 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/054 ,  H01L2924/00

Abstract: In order to provide a method of manufacturing a multilayer wiring substrate, a base member having a copper foil separably laminated thereon is prepared, and a solder resist layer is formed on the copper foil. Openings are formed in the solder resist layer, and a metal conductor portion is formed in each of the openings. By means of sputtering, a dissimilar metal layer is formed over the surface of the metal conductor portion and the entire surface of the solder resist layer. Copper electroplating is performed so as to form connection terminals and a conductor layer on the dissimilar metal layer. After a build-up step, the base material is removed, whereby the copper foil is exposed, and the exposed copper foil and the metal conductor portion are removed through etching, whereby the surfaces of the external connection terminals are exposed from the openings.

Abstract translation: 为了提供一种制造多层布线基板的方法，制备了具有可分离层压在其上的铜箔的基底构件，并且在铜箔上形成阻焊层。 在阻焊层中形成开口，并且在每个开口中形成金属导体部。 通过溅射，在金属导体部分的表面和阻焊层的整个表面上形成不同的金属层。 进行铜电镀，以在异种金属层上形成连接端子和导体层。 在堆积步骤之后，除去基材，由此露出铜箔，通过蚀刻去除暴露的铜箔和金属导体部分，从而使外部连接端子的表面从开口露出。

公开(公告)号：US20120111624A1

公开(公告)日：2012-05-10

申请号：US13288497

申请日：2011-11-03

Applicant: Shinnosuke MAEDA

Inventor： Shinnosuke MAEDA

IPC: H05K1/11

CPC classification number: H05K3/4682 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/09136 ,  H01L2924/00

Abstract: A multilayer wiring substrate has a main face and a back face, and a configuration in which a plurality of resin insulation layers and a plurality of conductor layers are laminated. A plurality of conductor layers provided on the side toward the back face in relation to a resin insulation layer serving as a center layer are formed such that the average of their area ratios becomes greater than the average of area ratios of a plurality of conductor layers provided on the side toward the main face in relation to the center layer. A plurality of resin insulation layers provided on the side toward the back face are formed such that the average of their thicknesses becomes greater than the average of thicknesses of a plurality of resin insulation layers provided on the side toward the main face.

Abstract translation: 多层布线基板具有主面和背面，以及层叠有多个树脂绝缘层和多个导体层的结构。 形成相对于作为中心层的树脂绝缘层在背面侧设置的多个导体层，使得它们的面积比的平均值大于设置的多个导体层的面积比的平均值 在相对于中心层的主面侧。 形成在背面侧的多个树脂绝缘层，使得其厚度的平均值大于设置在朝向主面的一侧的多个树脂绝缘层的厚度的平均值。

公开(公告)号：US20120018194A1

公开(公告)日：2012-01-26

申请号：US13184661

申请日：2011-07-18

Applicant: Shinnosuke MAEDA ,  Satoshi HIRANO ,  Yuuki SHIIBA

Inventor： Shinnosuke MAEDA ,  Satoshi HIRANO ,  Yuuki SHIIBA

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H05K3/0035 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1461 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0373 ,  H05K3/4644 ,  H05K2201/0209 ,  H05K2201/09827 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Disclosed is a manufacturing method of a multilayer wiring board. The multilayer wiring board includes an outer resin insulation layer made of an insulating resin material, containing a filler of inorganic filler and having an outer surface defining a chip mounting area to which an electronic chip is mounted with an underfill material filled in between the outer resin insulation layer and the electronic chip and holes through which conductor parts are exposed. The manufacturing method includes a hole forming step of forming the holes in the outer resin insulation layer by laser processing, a desmear treatment step of, after the hole forming step, removing smears from inside the holes of the outer resin insulation layer, and a filler reducing step of, after the desmear treatment step, reducing the amount of the filler exposed at the outer surface of the outer resin insulation layer.

Abstract translation: 公开了一种多层布线板的制造方法。 多层布线基板包括由绝缘树脂材料制成的外部树脂绝缘层，其包含无机填料的填料并且具有限定芯片安装区域的外表面，电子芯片安装在该芯片安装区域，底部填充材料填充在外部树脂 绝缘层以及导体部件露出的电子芯片和孔。 该制造方法包括：通过激光加工在外树脂绝缘层中形成孔的孔形成步骤，在孔形成步骤之后的去污处理步骤，从外树脂绝缘层的孔内部除去污迹，以及填料 在去污处理步骤之后，减少在外树脂绝缘层的外表面暴露的填料的量。

公开(公告)号：US20110155443A1

公开(公告)日：2011-06-30

申请号：US12979474

申请日：2010-12-28

Applicant: Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Tatsuya ITO ,  Satoshi HIRANO ,  Atsuhiko SUGIMOTO

Inventor： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Tatsuya ITO ,  Satoshi HIRANO ,  Atsuhiko SUGIMOTO

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K1/0298 ,  H01L21/4846 ,  H01L23/49822 ,  H01L2224/16225 ,  H05K1/09 ,  H05K1/111 ,  H05K1/113 ,  H05K3/0055 ,  H05K3/3452 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/0989 ,  H05K2201/099

Abstract: In a build-up step, a plurality of resin insulation layers and a plurality of conductive layers are alternately laminated in multilayer arrangement on a metal foil separably laminated on a side of a base material, thereby forming a wiring laminate portion. In a drilling step, a plurality of openings are formed in an outermost resin insulation layer through laser drilling so as to expose connection terminals. Subsequently, in a desmear step, smears from inside the openings are removed. In a base-material removing step performed after the build-up step, the base material is removed and the metal foil is exposed.

Abstract translation: 在堆积步骤中，将多个树脂绝缘层和多个导电层以多层布置交替层叠在可分离地层叠在基材侧上的金属箔上，从而形成布线层压体部分。 在钻井工序中，通过激光钻孔在最外层的树脂绝缘层上形成多个开口，露出连接端子。 随后，在去污步骤中，去除开口内部的污迹。 在堆积步骤之后执行的基材除去步骤中，除去基材并暴露金属箔。

公开(公告)号：US20100208442A1

公开(公告)日：2010-08-19

申请号：US12705776

申请日：2010-02-15

Applicant: Toshiya ASANO ,  Shinnosuke MAEDA

Inventor： Toshiya ASANO ,  Shinnosuke MAEDA

IPC: H05K7/00 ,  H05K3/30

CPC classification number: H05K1/0271 ,  H01L21/563 ,  H01L23/16 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/562 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K3/0058 ,  H05K2201/2009 ,  H05K2201/2018 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A wiring board assembly includes a rectangular plate-shaped wiring board having a plurality of resin insulation layers and conduction layers alternately laminated together to define opposite first and second main surfaces and a plurality of connection terminals arranged on the first main surface for surface contact with terminals of a chip and a rectangular frame-shaped reinforcing member fixed to the first main surface of the wiring board with the connection terminals exposed through an opening of the reinforcing member. The reinforcing member has a plurality of structural pieces separated by slits extending from an inner circumferential surface to an outer circumferential surface of the reinforcing member.

Abstract translation: 布线基板组件包括矩形板状布线板，其具有多个树脂绝缘层和交替层叠在一起以限定相对的第一和第二主表面的导电层，以及布置在第一主表面上用于与端子表面接触的多个连接端子 所述芯片和矩形框状加固件固定到所述布线板的所述第一主表面，所述连接端子通过所述加强件的开口暴露。 加强构件具有由从加强构件的内周面延伸到外周面的狭缝分隔开的多个结构件。

公开(公告)号：US09006580B2

公开(公告)日：2015-04-14

申请号：US13490850

申请日：2012-06-07

Applicant: Shinnosuke Maeda ,  Hajime Saiki ,  Satoshi Hirano

Inventor： Shinnosuke Maeda ,  Hajime Saiki ,  Satoshi Hirano

IPC: H05K1/03 ,  H05K3/02 ,  H05K3/10 ,  H05K3/40 ,  H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/544 ,  H01L21/683 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K3/4007 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/544 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K1/0269 ,  H05K1/113 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09781 ,  H05K2203/072 ,  H05K2203/1105 ,  Y10T29/49155

Abstract: Disclosed is a method of manufacturing a multilayer wiring substrate having a principal plane of the substrate and a rear plane thereof, having a structure such that a plurality of resin insulating layers and a plurality of conductor layers are laminated, and a plurality of chip component connecting terminals to which chip components are connectable are disposed on the principal plane of the substrate. This method has a feature including a plating layer forming process in which product plating layers which provide the plurality of chip component connecting terminals and a dummy plating layer on the surrounding of the product plating layers are formed on the surface of an exposed outermost resin insulating layer at the principal plane of the substrate. This method permits a thickness dispersion of the chip component connecting terminals to be suppressed and permits a connection reliability thereof to the chip components to be increased.

Abstract translation: 公开了一种多层布线基板的制造方法，该多层布线基板具有基板的主面及其背面，具有层叠多个树脂绝缘层和多个导体层的结构，并且多个芯片部件连接 芯片部件可连接的端子设置在基板的主平面上。 该方法具有包括镀层形成工艺的特征，其中在露出的最外层树脂绝缘层的表面上形成了在产品镀层周围形成有多个芯片部件连接端子和虚拟镀层的产品镀层 在基板的主平面上。 该方法能够抑制芯片部件连接端子的厚度分散，并且能够提高芯片部件的连接可靠性。

公开(公告)号：US08859077B2

公开(公告)日：2014-10-14

申请号：US13028588

申请日：2011-02-16

Applicant: Shinnosuke Maeda ,  Tetsuo Suzuki ,  Satoshi Hirano

Inventor： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Satoshi Hirano

IPC: B32B3/24 ,  H05K3/46 ,  H05K1/11 ,  H05K3/20

CPC classification number: H05K3/4682 ,  H05K1/112 ,  H05K3/205 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/099 ,  Y10T428/24331 ,  Y10T428/24339

Abstract: A plurality of openings are formed in a resin insulation layer on a bottom surface side of a wiring laminate portion which constitutes a multilayer wiring substrate. A plurality of motherboard connection terminals are disposed to correspond to the openings. The motherboard connection terminals are primarily comprised of a copper layer, and peripheral portions of terminal outer surfaces thereof are covered by the outermost resin insulation layer. A dissimilar metal layer made of at least one metal which is lower in etching rate than copper is formed between an inner main surface of the outermost resin insulation layer and peripheral portions of the terminal outer surfaces.

Abstract translation: 在构成多层布线基板的布线层叠体的底面侧的树脂绝缘层上形成有多个开口部。 多个主板连接端子被设置成对应于这些开口。 母板连接端子主要由铜层构成，其端子外表面的周边部分被最外层树脂绝缘层覆盖。 在最外层树脂绝缘层的内主表面和端子外表面的周边部分之间形成由蚀刻速率低于铜的至少一种金属制成的异种金属层。

公开(公告)号：US08707554B2

公开(公告)日：2014-04-29

申请号：US12979474

申请日：2010-12-28

Applicant: Shinnosuke Maeda ,  Tetsuo Suzuki ,  Takuya Hando ,  Tatsuya Ito ,  Satoshi Hirano ,  Atsuhiko Sugimoto

Inventor： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Takuya Hando ,  Tatsuya Ito ,  Satoshi Hirano ,  Atsuhiko Sugimoto

IPC: H01R9/00 ,  H05K3/00

CPC classification number: H05K1/0298 ,  H01L21/4846 ,  H01L23/49822 ,  H01L2224/16225 ,  H05K1/09 ,  H05K1/111 ,  H05K1/113 ,  H05K3/0055 ,  H05K3/3452 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/0989 ,  H05K2201/099

Abstract: In a build-up step, a plurality of resin insulation layers and a plurality of conductive layers are alternately laminated in multilayer arrangement on a metal foil separably laminated on a side of a base material, thereby forming a wiring laminate portion. In a drilling step, a plurality of openings are formed in an outermost resin insulation layer through laser drilling so as to expose connection terminals. Subsequently, in a desmear step, smears from inside the openings are removed. In a base-material removing step performed after the build-up step, the base material is removed and the metal foil is exposed.

Abstract translation: 在堆积步骤中，将多个树脂绝缘层和多个导电层以多层布置交替层叠在可分离地层叠在基材侧上的金属箔上，从而形成布线层压体部分。 在钻井工序中，通过激光钻孔在最外层的树脂绝缘层上形成多个开口，露出连接端子。 随后，在去污步骤中，去除开口内部的污迹。 在堆积步骤之后执行的基材除去步骤中，除去基材并暴露金属箔。