公开(公告)号：US20100170088A1

公开(公告)日：2010-07-08

申请号：US12725460

申请日：2010-03-17

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

IPC: H05K3/10

CPC classification number: H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product.

Abstract translation: 制造具有电镀通孔（PTH）芯层衬底和层叠多层盲孔的板的结构和方法。 可以实现比常规方法更多的盲孔堆叠层。 具有高密度芯层的板的制造方法包括以下：在制造PTH之后，填充在芯层的PTH内部的填充材料被部分地去除，直到PTH已经通过蚀刻达到适当的平坦凹陷; 然后进行图像转印和图案电镀，以在芯层基板正在形成电路层时填充并使凹陷部分达到所需厚度以形成铜焊盘（过镀层）; 最后使用无电镀铜和图案电镀制成产品。

公开(公告)号：US20090308527A1

公开(公告)日：2009-12-17

申请号：US12137553

申请日：2008-06-12

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Bo-Yu Tseng

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Bo-Yu Tseng

IPC: B32B38/10

CPC classification number: H05K3/427 ,  B32B37/025 ,  B32B38/10 ,  B32B2038/0016 ,  B32B2305/076 ,  B32B2311/00 ,  B32B2457/08 ,  C22C1/002 ,  H05K3/025 ,  H05K3/108 ,  H05K3/382 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/0361 ,  H05K2203/0384

Abstract: A method for fabricating a circuit trace on a core board having a buried hole is provided. The method includes: providing a carrier plate having a detachable metal layer, an etching barrier layer, and a metal layer sequentially stacked thereon; roughening the metal layer which can be completely roughened; laminating the bonded metal layer, the etching barrier layer, the detachable metal layer and the carrier plate onto a dielectric, wherein the metal layer faces and contacts with the dielectric; and then removing the carrier plate therefrom. As such, even if the dielectric is difficult to be completely roughened, the roughened metal layer can enhance the bondability between the metal layer and the dielectric. The metal layer is processed to become the circuit trace later.

Abstract translation: 提供了一种用于在具有掩埋孔的芯板上制造电路迹线的方法。 该方法包括：提供具有可分离的金属层，蚀刻阻挡层和顺序堆叠在其上的金属层的载体板; 使可以完全粗糙化的金属层变粗糙; 将接合的金属层，蚀刻阻挡层，可拆卸金属层和载体板层压到电介质上，其中金属层面对并与电介质接触; 然后从其移除载体板。 因此，即使电介质难以完全粗糙化，粗糙化的金属层也可以提高金属层与电介质的结合性。 金属层后处理成电路迹线。

公开(公告)号：US20080251386A1

公开(公告)日：2008-10-16

申请号：US11734274

申请日：2007-04-12

Applicant: Ting-Hao Lin

Inventor： Ting-Hao Lin

IPC: C25D5/02

CPC classification number: H05K3/423 ,  H05K3/0035 ,  H05K3/025 ,  H05K3/205 ,  H05K3/242 ,  H05K3/382 ,  H05K3/421 ,  H05K2201/09563 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/1152

Abstract: A manufacturing method of a non-etched circuit board is disclosed herein, which employs a metal substrate having a metal barrier layer and an electroplated copper layer to transmit an electrical current to form a circuit layer. A patterned photoresist layer is formed on the electroplated copper layer to define the location of the circuit layer and form circuits or conductive via on the board by electroplating. An electroplated nickel layer or an electroplated gold layer is further formed on the circuit layer for protecting the circuits and improving the fine line capability. During or after the process, the metal substrate, the metal barrier layer, and the electroplated copper layer are removed to enlarge the wiring space, so that a high-density circuit board can be obtained.

Abstract translation: 本文公开了一种未蚀刻电路板的制造方法，其采用具有金属阻挡层和电镀铜层的金属基板来传输电流以形成电路层。 在电镀铜层上形成图案化的光致抗蚀剂层以限定电路层的位置，并通过电镀在电路板上形成电路或导电通孔。 在电路层上进一步形成电镀镍层或电镀金层，以保护电路并提高细线能力。 在处理过程中或之后，去除金属基板，金属阻挡层和电镀铜层以扩大布线空间，从而可以获得高密度电路板。

公开(公告)号：US20070148970A1

公开(公告)日：2007-06-28

申请号：US11319874

申请日：2005-12-27

Applicant: Ting-Hao Lin ,  Chih-Wei Lee

Inventor： Ting-Hao Lin ,  Chih-Wei Lee

IPC: H01L21/44

CPC classification number: H05K3/427 ,  H05K3/062 ,  H05K3/243 ,  H05K2201/09545

Abstract: A method of fabricating circuitry without conductive circles has steps of providing a plate with multiple apertures defined therein, the plate and inner walls of the apertures are coated with a copper layer; the copper layers are coated with a photoresist layer, which is then covered with a protective film; partly removing the photoresist layer at the apertures; removing the protective film to expose the photoresist layer; electroplating the inner walls of the apertures with copper; exposing and developing the photoresist layers; and finally, etching the copper layers to form a circuit pattern without any conductive circles.

Abstract translation: 制造没有导电圆的电路的方法具有提供其中限定有多个孔的板的步骤，所述孔的板和内壁涂覆有铜层; 铜层被涂覆有光致抗蚀剂层，然后用保护膜覆盖; 部分地在孔处除去光致抗蚀剂层; 去除保护膜以暴露光致抗蚀剂层; 用铜电镀孔的内壁; 曝光和显影光刻胶层; 最后，蚀刻铜层以形成没有任何导电圆的电路图案。

公开(公告)号：US07234230B1

公开(公告)日：2007-06-26

申请号：US11319998

申请日：2005-12-27

Applicant: Ting-Hao Lin ,  Chung-Yuan Chen

Inventor： Ting-Hao Lin ,  Chung-Yuan Chen

IPC: H01R43/00

CPC classification number: H05K3/4691 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/4688 ,  H05K2203/065 ,  H05K2203/167 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

Abstract: A composite circuit board comprises multiple soft panels evenly mounted on a rigid panel. The soft panels are positioned on the rigid panel in proper alignment via locating pins on the rigid panel and corresponding holes in the soft panels. The soft panels are securely bonded to the rigid panel to form the composite circuit boards. The smaller size of the soft panels minimizes the alignment problems caused by the different heat expansion rates of the soft panel and the rigid panel.

Abstract translation: 复合电路板包括均匀地安装在刚性面板上的多个软面板。 柔性面板通过刚性面板上的定位销和软面板中的相应孔定位在刚性面板上，以适当对准。 软面板牢固地结合到刚性面板上以形成复合电路板。 较小尺寸的软面板使由柔性面板和刚性面板的不同热膨胀率引起的对准问题最小化。

公开(公告)号：US06830496B2

公开(公告)日：2004-12-14

申请号：US10349242

申请日：2003-01-22

Applicant: Ting-Hao Lin ,  Li-Wei Kuo ,  Ching-Lin Chang

Inventor： Ting-Hao Lin ,  Li-Wei Kuo ,  Ching-Lin Chang

IPC: H01J900

CPC classification number: H01L33/62 ,  H01L25/0753 ,  H01L33/641 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2924/12041 ,  H01L2924/00014

Abstract: A light emitting diode device comprises a copper substrate having multiple light emitting regions, multiple dies and encapsulation. Each light emitting region has a die pad and at least one electrode connected together and encapsulant covering the light emitting region. The dies are respectively mounted on the die pads and are wire bonded to the corresponding electrode or electrodes. A step defining a gap is applied to the substrate to form multiple light emitting regions, and each light emitting region has a die pad and electrodes. Therefore, the present invention can simplify the steps for fabricating die pad and electrodes to increase the production rate of LED devices or LED display modules.

Abstract translation: 发光二极管器件包括具有多个发光区域的铜衬底，多个管芯和封装。 每个发光区域具有管芯焊盘和连接在一起的至少一个电极和覆盖发光区域的密封剂。 模具分别安装在芯片焊盘上，并且引线键合到相应的电极或电极。 对衬底施加限定间隙的步骤以形成多个发光区域，并且每个发光区域具有管芯焊盘和电极。 因此，本发明可以简化制造管芯焊盘和电极的步骤，以增加LED器件或LED显示模块的生产率。

公开(公告)号：US5884396A

公开(公告)日：1999-03-23

申请号：US846857

申请日：1997-05-01

Applicant: Ting-hao Lin

Inventor： Ting-hao Lin

IPC: H01L23/31 ,  H05K3/20 ,  H01R43/00

CPC classification number: H01L23/3128 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K3/20 ,  Y10T29/49121

Abstract: The present invention relates to a TF-BGA method for manufacturing a packaging substrate, and includes steps of forming a single-sided circuit on a copper plate by electroplating, removing a layer of photoresist and sequentially laminating a dielectric layer and a metal plate on the copper plate, etching the copper plate, selectively applying a layer of solder resist, defining a cavity opening by punching, routing or etching, attaching a heat sink, forming dam rings and protecting the laminate by mold compound, attaching a die and bonding gold wires and encapsulating the cavity opening by encapsulate and attaching solder balls. In particular, a metal plate substitutes for a BT resin material to achieve low packaging cost and increasing the heat dissipating efficiency. A transfer flat type ball grid array method is employed to achieve an effect of fine circuitry and each single substrate is processed and tested individually. After the defective substrate units have been removed, the substrate units proved to be good are arranged in a long strip form and the borders thereof are molded to link in a latitudinal extension shape. A problem of the conventional entire strip of substrate set becoming useless when part of the substrate units are defective can be eliminated.

Abstract translation: 本发明涉及一种用于制造封装衬底的TF-BGA方法，包括以下步骤：通过电镀在铜板上形成单面电路，除去一层光致抗蚀剂，并依次层叠电介质层和金属板 铜板，蚀刻铜板，选择性地施加一层阻焊剂，通过冲压，布线或蚀刻，安装散热片，形成阻挡环并通过模塑化合物保护层压板，连接芯片和接合金线来限定空腔开口 并通过封装并附着焊球来封装空腔开口。 特别地，金属板代替BT树脂材料以实现低封装成本并增加散热效率。 采用转移平板式球栅阵列方法来实现精细电路的效果，并且单个基板被单独处理和测试。 在已经去除了有缺陷的基板单元之后，证明为良好的基板单元被布置成长条形，并且其边界被模制成以横向延伸形状连接。 可以消除当基板单元的一部分有缺陷时传统的整个基板组件变得无用的问题。

公开(公告)号：US5882957A

公开(公告)日：1999-03-16

申请号：US871471

申请日：1997-06-09

Applicant: Ting-hao Lin

Inventor： Ting-hao Lin

IPC: H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H05K3/20 ,  H01L21/44 ,  H01L21/50

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/24 ,  H01L23/36 ,  H01L2221/68345 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01028 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/20

Abstract: A BGA packaging method for an IC includes steps of providing a first dry film to a copper plate, plating nickel-copper to form circuits on one side of the copper plate, providing a second dry film, selectively plating nickel-gold, removing the dry films, providing an insulating layer, providing a back plate, attaching a chip, wire bonding, encapsulating the chip and wires with plastic, etching copper, providing solder resist and attaching solder balls. By this method, a packaged IC with excellent electrical characteristics and heat dissipation can be obtained through a simple procedure.

Abstract translation: 用于IC的BGA封装方法包括以下步骤：向铜板提供第一干膜，镀镍铜以在铜板的一侧上形成电路，提供第二干膜，选择性镀镍金，去除干 膜，提供绝缘层，提供背板，附接芯片，引线接合，用塑料封装芯片和电线，蚀刻铜，提供阻焊剂和附接焊球。 通过这种方法，可以通过简单的程序获得具有优异的电特性和散热的封装IC。

公开(公告)号：US08377815B2

公开(公告)日：2013-02-19

申请号：US13043463

申请日：2011-03-09

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

IPC: H01L21/44

CPC classification number: H01L24/13 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/00

Abstract: A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pad is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced.

Abstract translation: 公开了一种半导体负载板的制造方法。 该制造方法包括第一导电层形成步骤，第一图案化步骤，介电层形成步骤，钻孔步骤，第二导电层形成步骤，第二图案化步骤或两次图案化步骤，以及焊料连接步骤 。 在第二图案化步骤或二次图案化步骤中，在电介质层的开口中形成焊料焊盘，其中每个焊盘的高度高于电介质的高度，并且每个焊盘的宽度相等 达到或小于开口的最大宽度，使得在相同的区域中设置更宽的间隔，并且可以减少短路故障和电气干扰的问题。

公开(公告)号：US08312624B1

公开(公告)日：2012-11-20

申请号：US13304340

申请日：2011-11-24

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  De-Hao Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  De-Hao Lu

IPC: H05K3/02

CPC classification number: H05K3/427 ,  H05K1/0206 ,  H05K3/421 ,  H05K2203/025 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a heat dissipation structure of a printed circuit board includes: forming a barrier layer on the dimple in the first copper plating layer; forming a nickel plating layer; removing the nickel plating layer and the barrier layer on the dimple; forming a second copper plating layer to make the total height of the first copper plating layer and the second copper plating layer in the second opening higher than that of the first copper plating layer in the first opening; filling the dimple in the second copper plating layer with an etching-resistant material; removing the second copper plating layer; removing the nickel plating layer and the etching-resistant material to make the second copper plating layer in the second opening being at the same height as the first copper plating layer in the first opening; and forming the heat dissipation structure by photolithography.

Abstract translation: 制造印刷电路板的散热结构的方法包括：在第一镀铜层的凹坑上形成阻挡层; 形成镀镍层; 去除凹坑上的镀镍层和阻挡层; 形成第二镀铜层，使第二开口中的第一镀铜层和第二镀铜层的总高度高于第一开口中的第一镀铜层的总高度; 用耐腐蚀材料填充第二镀铜层中的凹坑; 去除所述第二镀铜层; 去除镀镍层和耐腐蚀材料，使得第二开口中的第二镀铜层处于与第一开口中的第一铜镀层相同的高度; 并通过光刻法形成散热结构。