公开(公告)号：US20210004256A1

公开(公告)日：2021-01-07

申请号：US17024619

申请日：2020-09-17

Applicant: ALTERA CORPORATION

Inventor： Jiefan Zhang ,  Abdel Hafiz Rabi ,  Allen Chen ,  Mark Jonathan Lewis

IPC: G06F9/455 ,  G06F9/54 ,  G06F15/78

Abstract: Techniques and mechanisms provide a flexible mapping for physical functions and virtual functions in an environment including virtual machines.

公开(公告)号：US20190079794A1

公开(公告)日：2019-03-14

申请号：US16190099

申请日：2018-11-13

Applicant: ALTERA CORPORATION

Inventor： Jiefan Zhang ,  Abdel Hafiz Rabi ,  Allen Chen ,  Mark Jonathan Lewis

IPC: G06F9/455 ,  G06F9/54 ,  G06F15/78

Abstract: Techniques and mechanisms provide a flexible mapping for physical functions and virtual functions in an environment including virtual machines.

公开(公告)号：US09768783B1

公开(公告)日：2017-09-19

申请号：US15183457

申请日：2016-06-15

Applicant: Altera Corporation

Inventor： Herman Schmit ,  Jiefan Zhang

IPC: H03K19/177 ,  H03K19/173 ,  G11C7/22 ,  G11C7/10

CPC classification number: H03K19/1737 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/106 ,  G11C7/22 ,  H03K3/02 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/1776

Abstract: Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other blocks. Configurable processing blocks may be configured to process data at a double data rate or a single data rate. Furthermore, configurable processing blocks that include accumulator circuitry may be configured to perform one accumulation at a single data rate or at a double data rate. Such configurable processing blocks may also be configured to perform two accumulations at a single data rate.

公开(公告)号：US11960921B2

公开(公告)日：2024-04-16

申请号：US18196270

申请日：2023-05-11

Applicant: Altera Corporation

Inventor： Abdel Hafiz Rabi ,  Allen Chen ,  Mark Jonathan Lewis ,  Jiefan Zhang

IPC: G06F13/40 ,  G06F9/455 ,  G06F13/28

CPC classification number: G06F9/45558 ,  G06F13/28 ,  G06F13/4022 ,  G06F2009/45595 ,  G06F2213/0038 ,  G06F2213/28

Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.

公开(公告)号：US20230325230A1

公开(公告)日：2023-10-12

申请号：US18196270

申请日：2023-05-11

Applicant: Altera Corporation

Inventor： Abdel Hafiz Rabi ,  Allen Chen ,  Mark Jonathan Lewis ,  Jiefan Zhang

IPC: G06F9/455 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F9/45558 ,  G06F13/4022 ,  G06F13/28 ,  G06F2213/0038 ,  G06F2213/28 ,  G06F2009/45595

Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.

公开(公告)号：US20210216354A1

公开(公告)日：2021-07-15

申请号：US17214522

申请日：2021-03-26

Applicant: Altera Corporation

Inventor： Abdel Hafiz Rabi ,  Allen Chen ,  Mark Jonathan Lewis ,  Jiefan Zhang

IPC: G06F9/455 ,  G06F13/40 ,  G06F13/28

Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.

公开(公告)号：US09588791B2

公开(公告)日：2017-03-07

申请号：US14697307

申请日：2015-04-27

Applicant: Altera Corporation

Inventor： Jiefan Zhang ,  Abdel Hafiz Rabi ,  Allen Chen ,  Mark Jonathan Lewis

IPC: G06F9/455 ,  G06F9/54 ,  G06F15/78

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F9/54 ,  G06F15/7867 ,  G06F15/7889

Abstract: Techniques and mechanisms provide a flexible mapping for physical functions and virtual functions in an environment including virtual machines.

Abstract translation: 技术和机制为包括虚拟机在内的环境中的物理功能和虚拟功能提供灵活的映射。

公开(公告)号：US09378043B1

公开(公告)日：2016-06-28

申请号：US14724089

申请日：2015-05-28

Applicant: Altera Corporation

Inventor： Jiefan Zhang ,  Alexander Kugel ,  Allen Chen ,  Mark Jonathan Lewis ,  Abdel Hafiz Rabi

IPC: G06F9/455 ,  G06F13/28 ,  G06F9/48

CPC classification number: G06F9/45558 ,  G06F9/45533 ,  G06F9/4881 ,  G06F13/28 ,  G06F2009/45579 ,  H04L49/70

Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The traffic at the NFV platform may be controlled by a distributed Quality of Service (QoS) manager. The distributed QoS manager may include multiple QoS modules each of which serves to perform priority queuing independently for its associated component or interface. For example, the NFV platform may include a first QoS module for arbitrating among multiple virtual machines, a second QoS module for performing priority queuing for data packets received at an external network port, a third QoS module for arbitrating among memory accesses at a coprocessor external memory interface, fourth QoS module for arbitrating accesses among multiple hardware acceleration slices, etc.

Abstract translation: 提供了网络功能虚拟化（NFV）的虚拟化平台。 虚拟化平台可以包括耦合到加速协处理器的主机处理器。 加速协处理器可以是可重构集成电路，以帮助为NFV提供改进的灵活性和敏捷性。 NFV平台上的流量可以由分布式服务质量（QoS）管理器来控制。 分布式QoS管理器可以包括多个QoS模块，每个QoS模块用于独立地为其相关联的组件或接口执行优先级排队。 例如，NFV平台可以包括用于在多个虚拟机之间进行仲裁的第一QoS模块，用于对在外部网络端口处接收的数据分组进行优先级排队的第二QoS模块，用于在协处理器外部的存储器访问之间进行仲裁的第三QoS模块 存储器接口，用于在多个硬件加速片之间仲裁访问的第四QoS模块等。