公开(公告)号：US11257677B2

公开(公告)日：2022-02-22

申请号：US16751691

申请日：2020-01-24

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik ,  Wenting Hou ,  Jianxin Lei ,  Chen Gong ,  Yong Cao

IPC: C23C14/56 ,  H01L21/285 ,  H01L21/768 ,  C23C14/14 ,  C23C14/24 ,  C23C14/06

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

公开(公告)号：US11164780B2

公开(公告)日：2021-11-02

申请号：US16435121

申请日：2019-06-07

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi You ,  He Ren ,  Mehul Naik ,  Yi Xu ,  Feng Chen

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02

Abstract: Methods and apparatus for an interconnect formed on a substrate and a method of forming the interconnect thereon. In embodiments, the methods include etching through a hard mask disposed atop a low-k dielectric layer to form a via through the low-k dielectric layer and expose a conductive surface; contacting the conductive surface with dilute hydrofluoric acid to remove contaminants therefrom; removing the hard mask disposed atop the low-k dielectric layer; and applying a remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface.

公开(公告)号：US20210233770A1

公开(公告)日：2021-07-29

申请号：US16751691

申请日：2020-01-24

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik ,  Wenting Hou ,  Jianxin Lei ,  Chen Gong ,  Yong Cao

IPC: H01L21/285 ,  H01L21/768 ,  C23C14/06 ,  C23C14/14 ,  C23C14/24 ,  C23C14/56

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

公开(公告)号：US10685849B1

公开(公告)日：2020-06-16

申请号：US16400737

申请日：2019-05-01

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC: H01L21/321 ,  H01L21/3213

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US10438849B2

公开(公告)日：2019-10-08

申请号：US15137245

申请日：2016-04-25

Applicant: APPLIED MATERIALS, INC.

Inventor： He Ren ,  Jie Zhou ,  Guannan Chen ,  Michael W. Stowell ,  Bencherki Mebarki ,  Mehul Naik ,  Srinivas D. Nemani ,  Nikolaos Bekiaris ,  Zhiyuan Wu

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: An integrated circuit is fabricated by chemical vapor deposition or atomic layer deposition of a metal film to metal film.

公开(公告)号：US20140287577A1

公开(公告)日：2014-09-25

申请号：US14211602

申请日：2014-03-14

Applicant: APPLIED Materials, Inc.

Inventor： Ismail T. Emesh ,  Roey Shaviv ,  Mehul Naik

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for producing interconnects on a workpiece includes obtaining a workpiece substrate having a feature, depositing a conductive layer in the feature, to partially or fully fill the feature, depositing a copper fill to completely fill the feature if the feature is partially filled by the conductive layer, applying a copper overburden, thermally treating the workpiece, and removing the overburden to expose the substrate and the metalized feature.

Abstract translation: 一种用于在工件上制造互连件的方法包括获得具有特征的工件衬底，在特征中沉积导电层以部分或全部填充该特征，如果该特征部分地由 导电层，施加铜覆盖层，热处理工件，以及去除覆盖层以暴露衬底和金属化特征。

公开(公告)号：US11967527B2

公开(公告)日：2024-04-23

申请号：US17843966

申请日：2022-06-18

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/7685 ,  H01L21/76892 ,  H01L23/5226

Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.

公开(公告)号：US20230326925A1

公开(公告)日：2023-10-12

申请号：US17715331

申请日：2022-04-07

Applicant: Applied Materials, Inc.

Inventor： Andrew Anthony Cockburn ,  Vanessa Pena ,  Daniel Philippe Cellier ,  John Tolle ,  Thomas Kirschenheiter ,  Wei Hong ,  Ellie Y. Yieh ,  Mehul Naik ,  Seshadri Ramaswami

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/66742

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

公开(公告)号：US11749532B2

公开(公告)日：2023-09-05

申请号：US17307383

申请日：2021-05-04

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  Chi Lu ,  He Ren ,  Mehul Naik

IPC: H01L21/3213 ,  H01L21/033 ,  H01J37/32 ,  H01L21/67 ,  H01L23/532

CPC classification number: H01L21/32136 ,  H01J37/32449 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/67069 ,  H01J37/32183 ,  H01J2237/3341 ,  H01L23/53242

Abstract: Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O2) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of O2 or chloride (Cl2) while supplying nitrogen (N2) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.

公开(公告)号：US11508617B2

公开(公告)日：2022-11-22

申请号：US16662200

申请日：2019-10-24

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  Chi Lu ,  He Ren ,  Chi-I Lang ,  Ho-yung David Hwang ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/203

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.