公开(公告)号：US11955382B2

公开(公告)日：2024-04-09

申请号：US17110818

申请日：2020-12-03

Applicant: Applied Materials, Inc.

Inventor： Kevin Kashefi ,  Alexander Jansen ,  Mehul Naik ,  He Ren ,  Lu Chen ,  Feng Chen

IPC: H01L21/76 ,  H01L21/67 ,  H01L21/768 ,  H01L21/687

CPC classification number: H01L21/76885 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/76829 ,  H01L21/76883 ,  H01L21/68707

Abstract: Methods and apparatus for forming a reverse selective etch stop layer are disclosed. Some embodiments of the disclosure provide interconnects with lower resistance than methods which utilize non-selective (e.g., blanket) etch stop layers. Some embodiments of the disclosure utilize reverse selective etch stop layers within a subtractive etch scheme. Some embodiments of the disclosure selectively deposit the etch stop layer by passivating the surface of the metal material.

公开(公告)号：US11615984B2

公开(公告)日：2023-03-28

申请号：US16848784

申请日：2020-04-14

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi You ,  He Ren ,  Naomi Yoshida ,  Nikolaos Bekiaris ,  Mehul Naik ,  Martin Jay Seamons ,  Jingmei Liang ,  Mei-Yee Shek

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.

公开(公告)号：US20220270871A1

公开(公告)日：2022-08-25

申请号：US17742712

申请日：2022-05-12

Applicant: Applied Materials, Inc.

Inventor： Xi Cen ,  Yakuan Yao ,  Yiming Lai ,  Kai Wu ,  Avgerinos V. Gelatos ,  David T. Or ,  Kevin Kashefi ,  Yu Lei ,  Lin Dong ,  He Ren ,  Yi Xu ,  Mehul Naik ,  Hao Chen ,  Mang-Mang Ling

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/768

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.

公开(公告)号：US10204764B2

公开(公告)日：2019-02-12

申请号：US14525555

申请日：2014-10-28

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Annamalai Lakshmanan ,  Kaushal K. Singh ,  Andrew Cockburn ,  Ludovic Godet ,  Paul F. Ma ,  Mehul Naik

IPC: C23C16/42 ,  H01J37/32 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3205 ,  C23C16/56 ,  H01L21/268

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide layer on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide layer in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer. In another embodiment, a method includes supplying a deposition gas mixture including at least a metal containing precursor and a reacting gas on a surface of a substrate, forming a plasma in the presence of the deposition gas mixture by exposure to microwave power, exposing the plasma to light radiation, and forming a metal silicide layer on the substrate from the deposition gas.

公开(公告)号：US09437479B2

公开(公告)日：2016-09-06

申请号：US14523302

申请日：2014-10-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Suketu A. Parikh ,  Mehul Naik

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/7682 ,  H01L21/7684 ,  H01L2221/1047

Abstract: Embodiments of methods for forming interconnect patterns on a substrate are provided herein. In some embodiments, a method for forming an interconnect pattern atop a substrate includes depositing a porous dielectric layer atop a cap layer and a plurality of spacers disposed atop the cap layer, wherein the cap layer is disposed atop a bulk dielectric layer and the bulk dielectric layer is disposed atop a substrate; removing a portion of the porous dielectric layer; removing the plurality of spacers to form features in the porous dielectric layer; and etching the cap layer to extend the features through the cap layer.

Abstract translation: 本文提供了在衬底上形成互连图案的方法的实施例。 在一些实施例中，用于在衬底顶部形成互连图案的方法包括在顶盖顶部沉积多孔电​​介质层，以及设置在顶盖顶部的多个间隔物，其中所述覆盖层设置在体电介质层的顶部， 层设置在基板的顶部; 去除所述多孔介电层的一部分; 去除所述多个间隔物以在所述多孔介电层中形成特征; 并且蚀刻所述盖层以通过所述盖层延伸所述特征。

公开(公告)号：US09425092B2

公开(公告)日：2016-08-23

申请号：US14211602

申请日：2014-03-14

Applicant: APPLIED Materials, Inc.

Inventor： Ismail T. Emesh ,  Roey Shaviv ,  Mehul Naik

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for producing interconnects on a workpiece includes obtaining a workpiece substrate having a feature, depositing a conductive layer in the feature, to partially or fully fill the feature, depositing a copper fill to completely fill the feature if the feature is partially filled by the conductive layer, applying a copper overburden, thermally treating the workpiece, and removing the overburden to expose the substrate and the metalized feature.

Abstract translation: 一种用于在工件上制造互连件的方法包括获得具有特征的工件衬底，在特征中沉积导电层以部分或全部填充该特征，如果该特征部分地由 导电层，施加铜覆盖层，热处理工件，以及去除覆盖层以暴露衬底和金属化特征。

公开(公告)号：US11776806B2

公开(公告)日：2023-10-03

申请号：US17742712

申请日：2022-05-12

Applicant: Applied Materials, Inc.

Inventor： Xi Cen ,  Yakuan Yao ,  Yiming Lai ,  Kai Wu ,  Avgerinos V. Gelatos ,  David T. Or ,  Kevin Kashefi ,  Yu Lei ,  Lin Dong ,  He Ren ,  Yi Xu ,  Mehul Naik ,  Hao Chen ,  Mang-Mang Ling

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/768

CPC classification number: H01L21/02063 ,  H01L21/0234 ,  H01L21/02244 ,  H01L21/02334 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/76814 ,  H01L21/76879

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.

公开(公告)号：US11626288B2

公开(公告)日：2023-04-11

申请号：US17389772

申请日：2021-07-30

Applicant: Applied Materials, Inc.

Inventor： Raymond Hung ,  Mehul Naik ,  Michael Haverty

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/47 ,  H01L29/40 ,  H01L29/417

Abstract: Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide. In some embodiments, a method may comprise selectively depositing a metal silicide layer on an Epi surface and adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function for a P type Epi surface may be adjusted to a value of approximately 5.0 eV and the work function for an N type Epi surface may be adjusted to a value of approximately 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to deposition of a contact etch stop layer and an activation anneal.

公开(公告)号：US11410885B2

公开(公告)日：2022-08-09

申请号：US16864623

申请日：2020-05-01

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522

Abstract: Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.

公开(公告)号：US20220130676A1

公开(公告)日：2022-04-28

申请号：US17569870

申请日：2022-01-06

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik ,  Wenting Hou ,  Jianxin Lei ,  Chen Gong ,  Yong Cao

IPC: H01L21/285 ,  H01L21/768 ,  C23C14/56 ,  C23C14/14 ,  C23C14/24 ,  C23C14/06

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.