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    Reduced-dimension via-land structure and method of making the same
    11.
    发明授权
    Reduced-dimension via-land structure and method of making the same 有权

    公开(公告)号：US10334728B2

    公开(公告)日：2019-06-25

    申请号：US15019776

    申请日：2016-02-09

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee ,  Po-Shu Peng

    IPC: H05K1/11 ,  H05K3/10 ,  H05K3/40 ,  H05K3/00

    Abstract: A package substrate includes a dielectric layer, a conductive via disposed in the dielectric layer, and a conductive pattern layer exposed from a first surface of the dielectric layer. The conductive pattern layer includes traces and a via land, the via land extends into the conductive via, and a circumferential portion of the via land is encompassed by the conductive via. A method of making a package substrate includes forming a conductive pattern layer including traces and a via land, providing a dielectric layer to cover the conductive pattern layer, and forming a via hole. Forming the via hole is performed by removing a portion of the dielectric layer and exposing a bottom surface of the via land and at least a portion of a side surface of the via land. A conductive material is applied into the via hole to form a conductive via covering the via land.

    Substrate, semiconductor device package and method of manufacturing the same
    13.
    发明授权
    Substrate, semiconductor device package and method of manufacturing the same 有权

    公开(公告)号：US12165963B2

    公开(公告)日：2024-12-10

    申请号：US18375140

    申请日：2023-09-29

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

    Semiconductor substrate, semiconductor package, and method for forming the same
    16.
    发明授权
    Semiconductor substrate, semiconductor package, and method for forming the same 有权

    公开(公告)号：US10665523B2

    公开(公告)日：2020-05-26

    申请号：US16038037

    申请日：2018-07-17

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

    IPC: H01L23/00 ,  H01L23/367 ,  H01L21/768 ,  H01L23/373

    Abstract: The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.

    Semiconductor package with chamfered pads
    20.
    发明授权
    Semiconductor package with chamfered pads 有权

    公开(公告)号：US11056435B2

    公开(公告)日：2021-07-06

    申请号：US15815351

    申请日：2017-11-16

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin Ho ,  Chung Chieh Chang ,  Ya Fang Chan ,  Chih-Cheng Lee

    IPC: H01L23/535 ,  H01L21/02 ,  H01L23/498 ,  H01L23/00

    Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device package. The substrate comprises a dielectric layer, a first conductive element adjacent to the dielectric layer, a second conductive element adjacent to the dielectric layer, and a third conductive element adjacent to the dielectric layer. The first conductive element has a first central axis in a first direction and a second central axis in a second direction. The first conductive element comprises a first chamfer and a second chamfer adjacent to the first chamfer. The second conductive element has a first central axis in the first direction and a second central axis in the second direction. The third conductive element has a first central axis in the first direction and a second central axis in the second direction. The first central axes of the first, second, and third conductive elements are substantially parallel to one another in the first direction and are misaligned from one another. The second central axes of the first and second conductive elements are substantially co-linear in the second direction. The second central axis of the third conductive element is substantially parallel to and misaligned from the second central axes of the first and second conductive elements. The first chamfer and the second chamfer are separated by at least one of the first central axis and the second central axis of the first conductive element and are substantially asymmetric.

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