公开(公告)号：US09692418B1

公开(公告)日：2017-06-27

申请号：US14464340

申请日：2014-08-20

Applicant: Altera Corporation

Inventor： David Lewis ,  Herman Henry Schmit ,  Carl Ebeling

IPC: H03K19/173 ,  H03K19/0175

CPC classification number: H03K19/017581 ,  H03K19/017509 ,  H03K19/018521 ,  H03K19/1737

Abstract: An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant.

公开(公告)号：US20190273504A1

公开(公告)日：2019-09-05

申请号：US16414451

申请日：2019-05-16

Applicant: Altera Corporation

Inventor： David Mendel ,  Carl Ebeling ,  Dana How ,  Mahesh Iyer

IPC: H03L7/23 ,  H03L7/093 ,  H03L7/099 ,  H03L7/089

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

公开(公告)号：US09922157B1

公开(公告)日：2018-03-20

申请号：US14802702

申请日：2015-07-17

Applicant: Altera Corporation

Inventor： Carl Ebeling ,  Herman Henry Schmit ,  Dana How ,  Mahesh A. Iyer ,  Saurabh Adya

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081

Abstract: A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.

公开(公告)号：US09218862B1

公开(公告)日：2015-12-22

申请号：US14251423

申请日：2014-04-11

Applicant: Altera Corporation

Inventor： Richard Arthur Grenier ,  Carl Ebeling

IPC: G11C8/00 ,  G11C8/16 ,  G11C7/18 ,  G11C8/12 ,  G11C11/412 ,  G11C7/10

CPC classification number: G11C8/16 ,  G11C7/1075 ,  G11C7/18 ,  G11C8/06 ,  G11C8/12 ,  G11C11/412

Abstract: An integrated circuit may have circuitry that includes a storage circuit, a processing circuit, and at least one state register to implement a finite-state machine. The storage circuit may store base addresses and output data for each state of the finite-state machine. The storage circuit may further store offset values that are based on the input data to the finite-state machine and the state transition from a current state to a next state caused by the input data. The processing circuit may compute the address of the storage circuit location where the output data of the next state is stored. The computation of this address may depend on the offset value and base address of the current state. The state register may receive the address from the processing circuit, store the address, and perform the corresponding memory access operation on the storage circuit.

Abstract translation: 集成电路可以具有包括存储电路，处理电路和用于实现有限状态机的至少一个状态寄存器的电路。 存储电路可以存储有限状态机的每个状态的基地址和输出数据。 存储电路还可以将基于输入数据的偏移值存储到有限状态机，以及由输入数据引起的从当前状态到下一状态的状态转换。 处理电路可以计算存储下一状态的输出数据的存储电路位置的地址。 该地址的计算可能取决于当前状态的偏移值和基址。 状态寄存器可以从处理电路接收地址，存储地址，并在存储电路上执行相应的存储器访问操作。