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    METHODS FOR SILICON RECESS STRUCTURES IN A SUBSTRATE BY UTILIZING A DOPING LAYER
    15.
    发明申请
    METHODS FOR SILICON RECESS STRUCTURES IN A SUBSTRATE BY UTILIZING A DOPING LAYER 有权
    通过使用掺杂层对基底中的硅回收结构的方法

    公开(公告)号：US20150118822A1

    公开(公告)日：2015-04-30

    申请号：US14068312

    申请日：2013-10-31

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Ying ZHANG ,  Hua CHUNG ,  Srinivas D. NEMANI ,  Ludovic GODET

    IPC: H01L21/762 ,  H01L21/265

    CPC classification number: H01L21/76224 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/6831 ,  H01L29/66795

    Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.

    Abstract translation: 本发明的实施例提供了一种用于在具有良好的工艺控制的衬底中形成硅凹陷结构的方法，特别适用于制造用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠。 在一个实施例中，在衬底中形成凹陷结构的方法包括蚀刻由形成在衬底中的第二部分限定的衬底的第一部分，直到形成在衬底中的掺杂层露出。

    MULTI-STEP PROCESS FOR FLOWABLE GAP-FILL FILM
    16.
    发明公开
    MULTI-STEP PROCESS FOR FLOWABLE GAP-FILL FILM 审中-公开

    公开(公告)号：US20240128121A1

    公开(公告)日：2024-04-18

    申请号：US18392534

    申请日：2023-12-21

    Applicant: Applied Materials, Inc.

    Inventor： Maximillian CLEMONS ,  Nikolaos BEKIARIS ,  Srinivas D. NEMANI

    IPC: H01L21/768 ,  H01J37/32 ,  H01L21/02

    CPC classification number: H01L21/76837 ,  H01J37/32009 ,  H01L21/02271 ,  H01J2237/3321

    Abstract: Generally, examples described herein relate to methods and processing systems for performing multiple processes in a same processing chamber on a flowable gap-fill film deposited on a substrate. In an example, a semiconductor processing system includes a processing chamber and a system controller. The system controller includes a processor and memory. The memory stores instructions, that when executed by the processor cause the system controller to: control a first process within the processing chamber performed on a substrate having thereon a film deposited by a flowable process, and control a second process within the process chamber performed on the substrate having thereon the film. The first process includes stabilizing bonds in the film to form a stabilized film. The second process includes densifying the stabilized film.

    ADDITIVE PATTERNING OF SEMICONDUCTOR FILM STACKS
    20.
    发明申请
    ADDITIVE PATTERNING OF SEMICONDUCTOR FILM STACKS 有权

    公开(公告)号：US20210035619A1

    公开(公告)日：2021-02-04

    申请号：US16525470

    申请日：2019-07-29

    Applicant: Applied Materials, Inc.

    Inventor： John O. DUKOVIC ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Praburam GOPALRAJA ,  Steven Hiloong WELCH ,  Bhargav S. CITLA

    IPC: G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

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