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    Method for forming embedded circuit
    11.
    发明授权
    Method for forming embedded circuit 失效
    嵌入式电路的形成方法

    公开(公告)号：US08171626B1

    公开(公告)日：2012-05-08

    申请号：US13155375

    申请日：2011-06-07

    Applicant: Cheng-Po Yu ,  Chi-Min Chang

    Inventor： Cheng-Po Yu ,  Chi-Min Chang

    IPC: H05K3/02 ,  H05K3/10 ,  H05K3/00 ,  H01R9/00 ,  H01R43/00

    CPC classification number: H05K3/465 ,  H05K3/107 ,  H05K2201/0347 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49155

    Abstract: A method for forming an embedded circuit is disclosed. First, a substrate including a dielectric layer is provided. Second, the dielectric layer is entirely covered by a dummy layer. Then, the dummy layer is patterned and a trench is formed in the dielectric layer at the same time. Later, a seed layer is formed to entirely cover the dummy layer and the trench. Next, the dummy layer is removed and the seed layer covering the dummy layer is removed, too. Afterwards, a metal layer is filled in the trench to form an embedded circuit embedded in the dielectric layer.

    Abstract translation: 公开了一种用于形成嵌入式电路的方法。 首先，提供包括电介质层的基板。 第二，介电层完全被虚拟层覆盖。 然后，对虚拟层进行图案化，同时在电介质层中形成沟槽。 之后，形成种子层以完全覆盖虚设层和沟槽。 接下来，去除虚拟层，并且去除覆盖虚拟层的种子层。 之后，在沟槽中填充金属层，形成嵌入电介质层的嵌入电路。

    CIRCUIT BOARD
    12.
    发明申请
    CIRCUIT BOARD 审中-公开
    电路板

    公开(公告)号：US20120031651A1

    公开(公告)日：2012-02-09

    申请号：US12944275

    申请日：2010-11-11

    Applicant: TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H05K1/02 ,  H05K1/18

    CPC classification number: H05K1/0203 ,  H05K1/056 ,  H05K3/3436 ,  H05K2201/0187 ,  H05K2201/10106

    Abstract: A circuit board including a circuit layer, a thermally conductive substrate, an insulation layer, and at least one thermally conductive material is provided. The thermally conductive substrate has a plane. The insulation layer is disposed between the circuit layer and the plane and partially covers the plane. The thermally conductive material covers the plane without covered by the insulation layer and is in contact with the thermally conductive substrate. The insulation layer exposes the thermally conductive material.

    Abstract translation: 提供了包括电路层，导热基板，绝缘层和至少一种导热材料的电路板。 导热基板具有平面。 绝缘层设置在电路层和平面之间，并部分覆盖平面。 导热材料覆盖该平面而不被绝缘层覆盖，并与导热基板接触。 绝缘层暴露导热材料。

    Method of fabricating substrate
    13.
    发明授权
    Method of fabricating substrate 有权
    制造基板的方法

    公开(公告)号：US07867908B2

    公开(公告)日：2011-01-11

    申请号：US12422428

    申请日：2009-04-13

    Applicant: Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

    Inventor： Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

    IPC: H01L21/302

    CPC classification number: H01L23/142 ,  H01L21/6835 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/202 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel.

    Abstract translation: 制造衬底的方法包括以下步骤。 首先，提供具有第一表面和第二表面的金属板。 执行第一半蚀刻工艺以将金属板的第一表面蚀刻到第一深度，使得在第一表面上形成第一图案化金属层。 接下来，将第一绝缘材料沉积在第一图案化金属层中的间隙中以形成第一绝缘体。 此后，执行第二半蚀刻工艺以将金属板的第二表面蚀刻到第二深度并且暴露第一绝缘体的至少一部分，使得在第二表面上形成第二图案化金属层。 第一深度和第二深度一起等于金属面板的厚度。

    METHOD FOR FORMING CIRCUIT BOARD STRUCTURE OF COMPOSITE MATERIAL
    14.
    发明申请
    METHOD FOR FORMING CIRCUIT BOARD STRUCTURE OF COMPOSITE MATERIAL 审中-公开
    形成复合材料电路板结构的方法

    公开(公告)号：US20100266752A1

    公开(公告)日：2010-10-21

    申请号：US12763224

    申请日：2010-04-20

    Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Wen-Fang Liu

    Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Wen-Fang Liu

    IPC: H05K3/10

    CPC classification number: H05K3/107 ,  H05K1/036 ,  H05K1/0373 ,  H05K3/181 ,  H05K3/184 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2201/0257 ,  H05K2203/0264 ,  H05K2203/107 ,  H05K2203/308

    Abstract: A method for forming a circuit board structure of composite material is disclosed. First, a composite material structure including a substrate and a composite material dielectric layer is provided. The composite material dielectric layer includes a catalyst dielectric layer contacting the substrate and at least one sacrificial layer contacting the catalyst dielectric layer. The sacrificial layer is insoluble in water. Later, the composite material dielectric layer is patterned and simultaneously catalyst particles are activated. Then, a conductive layer is formed on the activated catalyst particles. Afterwards, at least one sacrificial layer is removed.

    Abstract translation: 公开了一种形成复合材料的电路板结构的方法。 首先，提供包括基板和复合材料介电层的复合材料结构。 复合材料介电层包括与基底接触的催化剂介电层和与催化剂介电层接触的至少一个牺牲层。 牺牲层不溶于水。 之后，复合材料介电层被图案化，同时催化剂颗粒被激活。 然后，在活化的催化剂颗粒上形成导电层。 之后，去除至少一个牺牲层。

    Manufacturing method of circuit board
    15.
    发明授权
    Manufacturing method of circuit board 有权
    电路板的制造方法

    公开(公告)号：US08963019B2

    公开(公告)日：2015-02-24

    申请号：US13570251

    申请日：2012-08-09

    Applicant: Cheng-Po Yu ,  Shang-Feng Huang ,  Chang-Ming Lee ,  Young-Sheng Bai

    Inventor： Cheng-Po Yu ,  Shang-Feng Huang ,  Chang-Ming Lee ,  Young-Sheng Bai

    IPC: H05K1/11 ,  H05K3/00

    CPC classification number: H05K3/381 ,  H05K3/105 ,  H05K3/108 ,  H05K2201/0215 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/095 ,  H05K2203/1461

    Abstract: A circuit board and a manufacturing method thereof are provided. According to the method, a dielectric layer is formed on a dielectric substrate, and the dielectric layer contains active particles. A surface treatment is performed on a surface of the dielectric first conductive layer is formed on the activated surface of the dielectric layer. A conductive via is formed in the dielectric substrate and the dielectric layer. A patterned mask layer is formed on the first conductive layer, in which the patterned mask layer exposes the conductive via and a part of the first conductive layer. A second conductive layer is formed on the first conductive layer and conductive via exposed by the patterned mask layer. The patterned mask layer and the first conductive layer below the patterned mask layer are removed.

    Abstract translation: 提供一种电路板及其制造方法。 根据该方法，在电介质基板上形成介电层，电介质层含有活性粒子。 在电介质层的活化表面上形成电介质第一导电层的表面进行表面处理。 在电介质基板和电介质层中形成导电通孔。 图案化的掩模层形成在第一导电层上，其中图案化掩模层暴露导电通孔和第一导电层的一部分。 在第一导电层上形成第二导电层，并且由图案化掩模层暴露出导电通路。 图案化掩模层和图案化掩模层下面的第一导电层被去除。

    EMBEDDED WIRING BOARD AND A MANUFACTURING METHOD THEREOF
    17.
    发明申请
    EMBEDDED WIRING BOARD AND A MANUFACTURING METHOD THEREOF 有权
    嵌入式接线板及其制造方法

    公开(公告)号：US20120231179A1

    公开(公告)日：2012-09-13

    申请号：US13474735

    申请日：2012-05-18

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K3/00 ,  C25D5/02 ,  B05D3/06

    CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

    Abstract: An embedded wiring board includes an upper wiring layer, a lower wiring layer, an insulation layer, a first conductive pillar and a second conductive pillar. The upper wiring layer contains an upper pad, the lower wiring layer contains a lower pad, and the insulation layer contains an upper surface and a lower surface opposite to the upper surface. The upper pad is embedded in the upper surface and the lower pad is embedded in the lower surface. The first conductive pillar is located in the insulation layer and includes an end surface which is exposed by the upper surface. A height of the first conductive pillar relative to the upper surface is larger than a depth of the upper pad relative to the upper surface. In addition, the second conductive pillar is located in the insulation layer and is connected between the first conductive pillar and the lower pad.

    Abstract translation: 嵌入布线板包括上布线层，下布线层，绝缘层，第一导电柱和第二导电柱。 上布线层包含上焊盘，下布线层包含下焊盘，绝缘层包含与上表面相对的上表面和下表面。 上垫片嵌入在上表面中，下垫片嵌入下表面。 第一导电柱位于绝缘层中，并且包括由上表面暴露的端面。 第一导电柱相对于上表面的高度大于上垫相对于上表面的深度。 此外，第二导电柱位于绝缘层中并连接在第一导电柱和下垫之间。

    CIRCUIT STRUCTURE OF CIRCUIT BOARD
    18.
    发明申请
    CIRCUIT STRUCTURE OF CIRCUIT BOARD 有权
    电路板电路结构

    公开(公告)号：US20120067630A1

    公开(公告)日：2012-03-22

    申请号：US13305310

    申请日：2011-11-28

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K1/09 ,  H05K1/00

    CPC classification number: H05K3/107 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/061 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2203/0369 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits.

    Abstract translation: 电路板的电路结构包括电介质层，多个第一电路和多个第二电路。 电介质层具有表面和凹版图案。 第一电路设置在电介质层的表面上。 第二电路设置在电介质层的凹版图案中。 第二电路的线宽小于第一电路的线宽，并且相邻的第二电路中的每两个之间的距离比相邻的第一电路中的每两个之间的距离短。

    Process of fabricating circuit structure
    19.
    发明授权
    Process of fabricating circuit structure 有权
    制作电路结构的过程

    公开(公告)号：US07921550B2

    公开(公告)日：2011-04-12

    申请号：US12345474

    申请日：2008-12-29

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K3/00

    CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

    Abstract: A process for forming a circuit structure includes providing a first composite-layer structure at first. A second composite-layer structure is then provided. The first composite-layer structure, a second dielectric layer and the second composite-layer structure are pressed so that a second circuit pattern and an independent via pad are embedded in the second dielectric layer, and the second dielectric layer is connected to the first dielectric layer. A first carrier substrate and a second carrier substrate are removed to expose a first circuit pattern and the second circuit pattern. At least one first opening that passes through the second dielectric layer and exposes the independent via pad is formed, and the first opening is filled with a conductive material to form a second conductive via that connects the independent via pad and a second via pad.

    Abstract translation: 一种形成电路结构的工艺包括首先提供第一复合层结构。 然后提供第二复合层结构。 第一复合层结构，第二介电层和第二复合层结构被按压，使得第二电路图案和独立通孔焊盘嵌入第二电介质层中，并且第二电介质层连接到第一电介质层 层。 去除第一载体衬底和第二载体衬底以暴露第一电路图案和第二电路图案。 形成穿过第二电介质层并暴露独立通孔焊盘的至少一个第一开口，并且用导电材料填充第一开口以形成连接独立通孔焊盘和第二通孔焊盘的第二导电通孔。

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