公开(公告)号：US20170160947A1

公开(公告)日：2017-06-08

申请号：US15433888

申请日：2017-02-15

Applicant: Imagination Technologies Limited

Inventor： Adrian J. Anderson ,  Gary C. Wass ,  Gareth J. Davies

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0629 ,  G06F3/0658 ,  G06F3/0673 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/5016 ,  G06F9/542 ,  G06F9/544 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/251

Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

公开(公告)号：US09575900B2

公开(公告)日：2017-02-21

申请号：US14625719

申请日：2015-02-19

Applicant: Imagination Technologies Limited

Inventor： Adrian J. Anderson ,  Gary C. Wass ,  Gareth J. Davies

IPC: G06F9/30 ,  G06F12/10 ,  G06F9/38 ,  G06F9/54 ,  G06F13/28 ,  G06F9/50

CPC classification number: G06F3/0607 ,  G06F3/0629 ,  G06F3/0658 ,  G06F3/0673 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/5016 ,  G06F9/542 ,  G06F9/544 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/251

Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

Abstract translation: 描述用于在数字信号处理系统中传送数据的技术。 在一个示例中，数字信号处理系统包括多个固定功能加速器，每个固定功能加速器均连接到存储器访问控制器，并且每个被配置为从存储器件读取数据，对数据执行一个或多个操作，并将数据写入存储器 设备。 为了避免将固定功能加速器硬连接在一起，并且为了提供可配置的数字信号处理系统，多线程处理器控制固定功能加速器和存储器之间的数据传输。 每个处理器线程被分配给存储器访问通道，并且线程被配置为检测事件的发生，并且响应于此，控制存储器访问控制器以使得所选择的固定功能加速器能够从数据读取数据或将数据写入到 存储器件通过其存储器访问通道。

公开(公告)号：US20160294597A1

公开(公告)日：2016-10-06

申请号：US15181687

申请日：2016-06-14

Applicant: Imagination Technologies Limited

Inventor： Mohammed El-Hajjar ,  Paul Murrin ,  Adrian J. Anderson

IPC: H04L27/26

CPC classification number: H04L27/2647 ,  H03M13/41 ,  H04L1/0054 ,  H04L1/06 ,  H04L1/0618 ,  H04L25/067 ,  H04L27/38

Abstract: Methods and apparatus for efficient demapping of constellations are described. In an embodiment, these methods may be implemented within a digital communications receiver, such as a Digital Terrestrial Television receiver. The method reduces the number of distance metric calculations which are required to calculate soft information in the demapper by locating the closest constellation point to the received symbol. This closest constellation point is identified based on a comparison of distance metrics which are calculated parallel to either the I- or Q-axis. The number of distance metric calculations may be reduced still further by identifying a local minimum constellation point for each bit in the received symbol and these constellation points are identified using a similar method to the closest constellation point. Where the system uses rotated constellations, the received symbol may be unrotated before any constellation points are identified.

公开(公告)号：US20130329838A1

公开(公告)日：2013-12-12

申请号：US13760361

申请日：2013-02-06

Applicant: IMAGINATION TECHNOLOGIES LIMITED

Inventor： Mohammed El-Hajjar ,  Paul Murrin ,  Adrian J. Anderson

IPC: H04L1/00

CPC classification number: H04L27/2647 ,  H03M13/41 ,  H04L1/0054 ,  H04L1/06 ,  H04L1/0618 ,  H04L25/067 ,  H04L27/38

Abstract: Methods and apparatus for efficient demapping of constellations are described. In an embodiment, these methods may be implemented within a digital communications receiver, such as a Digital Terrestrial Television receiver. The method reduces the number of distance metric calculations which are required to calculate soft information in the demapper by locating the closest constellation point to the received symbol. This closest constellation point is identified based on a comparison of distance metrics which are calculated parallel to either the I- or Q-axis. The number of distance metric calculations may be reduced still further by identifying a local minimum constellation point for each bit in the received symbol and these constellation points are identified using a similar method to the closest constellation point. Where the system uses rotated constellations, the received symbol may be unrotated before any constellation points are identified.

Abstract translation: 描述了有效地拆分星座的方法和装置。 在一个实施例中，这些方法可以在诸如数字地面电视接收机的数字通信接收机内实现。 该方法减少了通过将最接近的星座点定位到接收到的符号来计算解映射器中的软信息所需的距离度量计算的数量。 基于与I轴或Q轴平行计算的距离度量的比较来识别最接近的星座点。 通过识别接收到的符号中的每个位的局部最小星座点，可以进一步减少距离度量计算的数量，并且使用与最接近的星座点类似的方法来识别这些星座点。 在系统使用旋转星座的地方，在识别出任何星座点之前，接收到的符号可能未旋转。

公开(公告)号：US20220075723A1

公开(公告)日：2022-03-10

申请号：US17529954

申请日：2021-11-18

Applicant: Imagination Technologies Limited

Inventor： Paul Murrin ,  Adrian J. Anderson ,  Mohammed El-Hajjar

IPC: G06F12/06 ,  H03M13/27 ,  H03M13/00

Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.

公开(公告)号：US10387155B2

公开(公告)日：2019-08-20

申请号：US15079269

申请日：2016-03-24

Applicant: Imagination Technologies Limited

Inventor： Paul Murrin ,  Gareth Davies ,  Adrian J. Anderson

IPC: G06F9/30 ,  G06F15/76 ,  G06F15/167

Abstract: A processing system includes a program processor for executing a program, and a dedicated processor for executing operations of a particular type (e.g. vector processing operations). The program processor uses an interfacing module and a group of two or more register banks to offload operations of the particular type to the dedicated processor for execution thereon. While the dedicated processor is accessing one register bank for executing a current operation, the interfacing module can concurrently load data for a subsequent operation into a different one of the register banks. The use of multiple register banks allows the dedicated processor to spend a greater proportion of its time executing operations.

公开(公告)号：US09684592B2

公开(公告)日：2017-06-20

申请号：US15357682

申请日：2016-11-21

Applicant: Imagination Technologies Limited

Inventor： Adrian J. Anderson

IPC: G06F13/28 ,  G06F12/06 ,  G11C7/10 ,  G06F12/1009

CPC classification number: G06F12/063 ,  G06F12/1009 ,  G06F13/28 ,  G06F2212/1016 ,  G11C7/1072

Abstract: Memory address generation for digital signal processing is described. In one example, a digital signal processing system-on-chip utilizes an on-chip memory space that is shared between functional blocks of the system. An on-chip DMA controller comprises an address generator that can generate sequences of read and write memory addresses for data items being transferred between the on-chip memory and a paged memory device, or internally within the system. The address generator is configurable and can generate non-linear sequences for the read and/or write addresses. This enables aspects of interleaving/deinterleaving operations to be performed as part of a data transfer between internal or paged memory. As a result, a dedicated memory for interleaving operations is not required. In further examples, the address generator can be configured to generate read and/or write addresses that take into account limitations of particular memory devices when performing interleaving, such as DRAM.

公开(公告)号：US20170068616A1

公开(公告)日：2017-03-09

申请号：US15357682

申请日：2016-11-21

Applicant: Imagination Technologies Limited

Inventor： Adrian J. Anderson

IPC: G06F12/06 ,  G06F13/28

CPC classification number: G06F12/063 ,  G06F12/1009 ,  G06F13/28 ,  G06F2212/1016 ,  G11C7/1072

Abstract: Memory address generation for digital signal processing is described. In one example, a digital signal processing system-on-chip utilises an on-chip memory space that is shared between functional blocks of the system. An on-chip DMA controller comprises an address generator that can generate sequences of read and write memory addresses for data items being transferred between the on-chip memory and a paged memory device, or internally within the system. The address generator is configurable and can generate non-linear sequences for the read and/or write addresses. This enables aspects of interleaving/deinterleaving operations to be performed as part of a data transfer between internal or paged memory. As a result, a dedicated memory for interleaving operations is not required. In further examples, the address generator can be configured to generate read and/or write addresses that take into account limitations of particular memory devices when performing interleaving, such as DRAM.

Abstract translation: 描述了用于数字信号处理的存储器地址生成。 在一个示例中，数字信号处理片上系统利用在系统的功能块之间共享的片上存储器空间。 片上DMA控制器包括地址发生器，其可以为在片上存储器和分页存储器设备之间或系统内部传输的数据项生成读和写存储器地址的序列。 地址生成器是可配置的，并且可以为读取和/或写入地址生成非线性序列。 这使得交织/解交织操作的方面能够作为内部或分页存储器之间的数据传送的一部分来执行。 结果，不需要用于交织操作的专用存储器。 在另外的示例中，地址生成器可以被配置为产生读/写地址，其在执行诸如DRAM的交织时考虑特定存储器件的限制。

公开(公告)号：US09391739B2

公开(公告)日：2016-07-12

申请号：US14617648

申请日：2015-02-09

Applicant: Imagination Technologies Limited

Inventor： Mohammed El-Hajjar ,  Paul Murrin ,  Adrian J. Anderson

IPC: H04L27/00 ,  H04L1/00 ,  H04L25/06 ,  H04L27/38 ,  H04L27/26

CPC classification number: H04L27/2647 ,  H03M13/41 ,  H04L1/0054 ,  H04L1/06 ,  H04L1/0618 ,  H04L25/067 ,  H04L27/38

Abstract: Methods and apparatus for efficient demapping of constellations are described. In an embodiment, these methods may be implemented within a digital communications receiver, such as a Digital Terrestrial Television receiver. The method reduces the number of distance metric calculations which are required to calculate soft information in the demapper by locating the closest constellation point to the received symbol. This closest constellation point is identified based on a comparison of distance metrics which are calculated parallel to either the I- or Q-axis. The number of distance metric calculations may be reduced still further by identifying a local minimum constellation point for each bit in the received symbol and these constellation points are identified using a similar method to the closest constellation point. Where the system uses rotated constellations, the received symbol may be unrotated before any constellation points are identified.

公开(公告)号：US20150161058A1

公开(公告)日：2015-06-11

申请号：US14625719

申请日：2015-02-19

Applicant: Imagination Technologies Limited

Inventor： Adrian J. Anderson ,  Gary C. Wass ,  Gareth J. Davies

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/50

CPC classification number: G06F3/0607 ,  G06F3/0629 ,  G06F3/0658 ,  G06F3/0673 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/5016 ,  G06F9/542 ,  G06F9/544 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/251

Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

Abstract translation: 描述用于在数字信号处理系统中传送数据的技术。 在一个示例中，数字信号处理系统包括多个固定功能加速器，每个固定功能加速器均连接到存储器访问控制器，并且每个被配置为从存储器件读取数据，对数据执行一个或多个操作，并将数据写入存储器 设备。 为了避免将固定功能加速器硬连接在一起，并且为了提供可配置的数字信号处理系统，多线程处理器控制固定功能加速器和存储器之间的数据传输。 每个处理器线程被分配给存储器访问通道，并且线程被配置为检测事件的发生，并且响应于此，控制存储器访问控制器以使得所选择的固定功能加速器能够从数据读取数据或将数据写入到 存储器件通过其存储器访问通道。