-
公开(公告)号：US10296456B2
公开(公告)日：2019-05-21
申请号：US13794796
申请日：2013-03-12
Applicant: Imagination Technologies Limited
Inventor： Paul Murrin , Adrian J. Anderson , Mohammed El-Hajjar
Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.
-
公开(公告)号：US20200242029A1
公开(公告)日：2020-07-30
申请号：US16845303
申请日：2020-04-10
Applicant: Imagination Technologies Limited
Inventor： Paul Murrin , Adrian J. Anderson , Mohammed El-Hajjar
Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.
-
公开(公告)号：US10657050B2
公开(公告)日：2020-05-19
申请号：US16381268
申请日：2019-04-11
Applicant: Imagination Technologies Limited
Inventor： Paul Murrin , Adrian J. Anderson , Mohammed El-Hajjar
Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.
-
公开(公告)号：US20190220199A1
公开(公告)日：2019-07-18
申请号：US16363587
申请日：2019-03-25
Applicant: Imagination Technologies Limited
Inventor： Adrian J. Anderson , Gary C. Wass , Gareth J. Davies
CPC classification number: G06F3/0607 , G06F3/0629 , G06F3/0658 , G06F3/0673 , G06F9/3009 , G06F9/3851 , G06F9/5016 , G06F9/542 , G06F9/544 , G06F12/1081 , G06F13/28 , G06F2212/251
Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
-
公开(公告)号：US20160283439A1
公开(公告)日：2016-09-29
申请号：US15081007
申请日：2016-03-25
Applicant: Imagination Technologies Limited
Inventor： Paul Murrin , Gareth Davies , Adrian J. Anderson
CPC classification number: G06F15/8007 , G06F9/30036 , G06F9/3012 , G06F9/381 , G06F9/3887
Abstract: A SIMD processing module is provided, comprising multiple vector processing units (“VUs”), which can be used to execute an instruction on respective parts (or “subvectors”) within a vector. A control unit determines a vector position indication for each of the VUs to indicate which part of the vector that VU is to execute the instruction on. Therefore, the vector is conceptually divided into subvectors with the respective VUs executing the instruction on the respective subvectors in parallel. Each VU can then execute the instruction as intended, but only on a subsection of the whole vector. This allows an instruction that is written for execution on an n-way VU to be executed by multiple n-way VUs, each starting at different points of the vector, such that the instruction can be executed on more than n of the data items of the vector in parallel.
Abstract translation: 提供了一种SIMD处理模块，其包括多个向量处理单元（“VU”），其可用于对向量内的相应部分（或“子向量”）执行指令。 控制单元确定每个VU的向量位置指示，以指示VU要执行指令的向量的哪一部分。 因此，向量在概念上被划分为子向量，各个VU并行地在各个子向量上执行指令。 然后，每个VU可以按照预期的方式执行指令，但只能在整个向量的子部分上执行。 这允许在n路VU上写入用于执行的指令由多个n路VU执行，每个N个VU从矢量的不同点开始，使得指令可以在多于n个VU的数据项上执行 矢量并行。
-
Patent Agency Ranking
公开(公告)号：US20150155973A1
公开(公告)日：2015-06-04
申请号：US14617648
申请日：2015-02-09
Applicant: Imagination Technologies Limited
Inventor： Mohammed El-Hajjar , Paul Murrin , Adrian J. Anderson
IPC: H04L1/00
CPC classification number: H04L27/2647 , H03M13/41 , H04L1/0054 , H04L1/06 , H04L1/0618 , H04L25/067 , H04L27/38
Abstract: Methods and apparatus for efficient demapping of constellations are described. In an embodiment, these methods may be implemented within a digital communications receiver, such as a Digital Terrestrial Television receiver. The method reduces the number of distance metric calculations which are required to calculate soft information in the demapper by locating the closest constellation point to the received symbol. This closest constellation point is identified based on a comparison of distance metrics which are calculated parallel to either the I- or Q-axis. The number of distance metric calculations may be reduced still further by identifying a local minimum constellation point for each bit in the received symbol and these constellation points are identified using a similar method to the closest constellation point. Where the system uses rotated constellations, the received symbol may be unrotated before any constellation points are identified.
Abstract translation: 描述了有效地拆分星座的方法和装置。 在一个实施例中，这些方法可以在诸如数字地面电视接收机的数字通信接收机内实现。 该方法减少了通过将最接近的星座点定位到接收到的符号来计算解映射器中的软信息所需的距离度量计算的数量。 基于与I轴或Q轴平行计算的距离度量的比较来识别最接近的星座点。 通过识别接收到的符号中的每个位的局部最小星座点，可以进一步减少距离度量计算的数量，并且使用与最接近的星座点类似的方法来识别这些星座点。 在系统使用旋转星座的地方，在识别出任何星座点之前，接收到的符号可能未旋转。
-
7.发明申请公开(公告)号：US20140068168A1
公开(公告)日：2014-03-06
申请号：US13794796
申请日：2013-03-12
Applicant: IMAGINATION TECHNOLOGIES LIMITED
Inventor： Paul Murrin , Adrian J. Anderson , Mohammed El-Hajjar
IPC: G06F12/06
CPC classification number: G06F12/0607 , H03M13/2707 , H03M13/276 , H03M13/6505
Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.
Abstract translation: 描述了基于平铺的交错和行交错数据的解交织。 在一个示例中，解交织被分为两个存储器传送级，第一级从片上存储器到DRAM，第二级从DRAM到片上存储器。 每个阶段在行列交织的数据块的一部分上进行操作，并重新命令数据项，使得第二级的输出包括解交织的数据。 在第一阶段，根据存储器读取地址的非线性序列从片上存储器读取数据项并写入DRAM。 在第二阶段中，根据线性地址序列的突发从DRAM读出数据项，这些片段有效利用DRAM接口，并根据存储器写地址的非线性序列写回到片上存储器。
-
公开(公告)号：US11755474B2
公开(公告)日：2023-09-12
申请号：US17529954
申请日：2021-11-18
Applicant: Imagination Technologies Limited
Inventor： Paul Murrin , Adrian J. Anderson , Mohammed El-Hajjar
CPC classification number: G06F12/0607 , H03M13/276 , H03M13/2707 , H03M13/6505
Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.
-
公开(公告)号：US20190236006A1
公开(公告)日：2019-08-01
申请号：US16381268
申请日：2019-04-11
Applicant: Imagination Technologies Limited
Inventor： Paul Murrin , Adrian J. Anderson , Mohammed El-Hajjar
CPC classification number: G06F12/0607 , H03M13/2707 , H03M13/276 , H03M13/6505
Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.
-
公开(公告)号：US10268377B2
公开(公告)日：2019-04-23
申请号：US15433888
申请日：2017-02-15
Applicant: Imagination Technologies Limited
Inventor： Adrian J. Anderson , Gary C. Wass , Gareth J. Davies
Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
-
-
-
-
-
-
-
-
-
Search Results
27
records
(took 0.02 seconds)
