公开(公告)号：US09793255B2

公开(公告)日：2017-10-17

申请号：US14595669

申请日：2015-01-13

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Ralf Otremba ,  Hans-Joachim Schulze ,  Guenther Ruhl ,  Hans-Joerg Timme

IPC: H01L29/06 ,  H01L27/02 ,  H01L27/088 ,  H01L27/06 ,  H01L23/427 ,  H01L23/367 ,  H01L29/49 ,  H01L29/78 ,  H01L23/525 ,  H01L29/861 ,  H01L29/739

CPC classification number: H01L27/0248 ,  H01L23/3677 ,  H01L23/4275 ,  H01L23/525 ,  H01L27/0676 ,  H01L27/088 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device includes a wiring structure adjoining at least one side of a semiconductor body and comprising at least one electrically conductive compound. The power semiconductor device further includes a cooling material in the wiring structure. The cooling material is characterized by a change in structure by means of absorption of energy at a temperature TC ranging between 150° C. and 400° C.

公开(公告)号：US09331060B2

公开(公告)日：2016-05-03

申请号：US14617797

申请日：2015-02-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Joachim Mahler ,  Johannes Lodermeyer

IPC: H01L25/00 ,  H01L23/492 ,  H01L21/48 ,  H01L23/538 ,  H01L21/56 ,  H01L25/07 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/071 ,  H01L25/072 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24135 ,  H01L2224/245 ,  H01L2224/40105 ,  H01L2224/40227 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.

公开(公告)号：US09196577B2

公开(公告)日：2015-11-24

申请号：US14151110

申请日：2014-01-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Höglauer ,  Jürgen Schredl ,  Xaver Schlögel ,  Klaus Schiess

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.

Abstract translation: 半导体封装装置包括晶体管器件，其包括包括源电极和栅电极的第一侧，具有第一表面的管芯焊盘和具有第一表面的引线。 第一导电构件设置在源电极和管芯焊盘的第一表面之间，并将源极与管芯焊盘的第一表面隔开一定距离，该距离大于栅电极与第一表面之间的距离 铅。

公开(公告)号：US09184066B2

公开(公告)日：2015-11-10

申请号：US13678577

申请日：2012-11-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess ,  Bernd Roemer ,  Edward Fuergut

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/495 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099

Abstract: A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括：载体; 芯片，其设置在所述载体上方，所述芯片包括一个或多个接触焊盘，其中所述一个或多个接触焊盘的第一接触焊盘与所述载体电接触; 至少部分地围绕所述芯片的第一封装材料; 以及至少部分地围绕所述第一包封材料的第二包封材料。

公开(公告)号：US09099454B2

公开(公告)日：2015-08-04

申请号：US13964153

申请日：2013-08-12

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Veronika Huber ,  Thomas Kilger ,  Ralf Otremba ,  Bernd Stadler ,  Dominic Maier ,  Klaus Schiess ,  Andreas Schlögl ,  Uwe Wahl

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/36 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L21/561 ,  H01L21/568 ,  H01L23/36 ,  H01L23/49562 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L27/14618 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/85 ,  H01L2224/96 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00014

Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Abstract translation: 通过在模具的第一侧提供具有端子的半导体模具来制造半导体封装，在模具的相对的第二侧提供耦合到模具的材料，并将模具嵌入模制化合物中，使得模具被覆盖 通过除第一面以外的所有侧面的模塑料。 模塑料在靠近模具的第二侧的模塑料的一侧变细，以在模具的第二面露出材料，而不暴露模具的第二面。 在模具的第一侧上的端子形成电连接。 在晶体管管芯的情况下，端子可以是源极端子，并且晶体管管芯可以源极地附接到诸如引线框架的管芯焊盘的金属块。

公开(公告)号：US20150145112A1

公开(公告)日：2015-05-28

申请号：US14091917

申请日：2013-11-27

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba

IPC: H01L23/31 ,  H01L23/495

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In an embodiment, an electronic component includes a housing, a die pad having a first surface and a second surface opposing the first surface, a first high voltage semiconductor device arranged on the first surface of the die pad, a further semiconductor device arranged on the second surface of the die pad and a conductive connection between the first high voltage semiconductor device and the further semiconductor device. The conductive connection is surrounded by the housing and includes a portion arranged adjacent the die pad.

Abstract translation: 在一个实施例中，电子部件包括壳体，具有第一表面和与第一表面相对的第二表面的管芯焊盘，布置在管芯焊盘的第一表面上的第一高电压半导体器件， 芯片焊盘的第二表面和第一高压半导体器件与另外的半导体器件之间的导电连接。 导电连接被壳体包围，并且包括邻近管芯焊盘的部分。

公开(公告)号：US20150060878A1

公开(公告)日：2015-03-05

申请号：US14535138

申请日：2014-11-06

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L23/495

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L29/2003 ,  H01L29/78 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/85801 ,  H01L2224/8585 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.

Abstract translation: 根据本发明的实施例，半导体封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘和多个引线的第二引线框架。 第二模板设置在第一模板上。 半导体芯片设置在第二裸片上。 半导体芯片在面向第二引线框架的第一面上具有多个接触区域。 多个接触区域耦合到多个引线。

公开(公告)号：US20150041967A1

公开(公告)日：2015-02-12

申请号：US13964153

申请日：2013-08-12

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Veronika Huber ,  Thomas Kilger ,  Ralf Otremba ,  Bernd Stadler ,  Dominic Maier ,  Klaus Schiess ,  Andreas Schlögl ,  Uwe Wahl

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/561 ,  H01L21/568 ,  H01L23/36 ,  H01L23/49562 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L27/14618 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/85 ,  H01L2224/96 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00014

Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Abstract translation: 通过在模具的第一侧提供具有端子的半导体模具来制造半导体封装，在模具的相对的第二侧提供耦合到模具的材料，并将模具嵌入模制化合物中，使得模具被覆盖 通过除第一面以外的所有侧面的模塑料。 模塑料在靠近模具的第二侧的模塑料的一侧变细，以在模具的第二面露出材料，而不暴露模具的第二面。 在模具的第一侧上的端子形成电连接。 在晶体管管芯的情况下，端子可以是源极端子，并且晶体管管芯可以源极地附接到诸如引线框架的管芯焊盘的金属块。

公开(公告)号：US20150041859A1

公开(公告)日：2015-02-12

申请号：US13962622

申请日：2013-08-08

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Höglauer

IPC: H01L23/522 ,  H01L29/778

CPC classification number: H01L23/5226 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/48091 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/0761 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09972 ,  H01L2924/00014

Abstract: A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer.

Abstract translation: 再分配板包括：第一导电层，包括用于低电压信号的再分配结构;第二导电层，包括用于高电压信号的再分配结构;以及非导电层。 第二导电层通过非导电层与第一导电层间隔开。 再分配板还包括从再分布板的安装表面延伸到第二导电层的导电连接器。 导电连接器被第一导电层的低电压迹线围绕。

公开(公告)号：US20140151717A1

公开(公告)日：2014-06-05

申请号：US13705041

申请日：2012-12-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba

IPC: H01L23/495 ,  H01L21/50 ,  H01L29/16

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L23/49513 ,  H01L23/49562 ,  H01L29/1608 ,  H01L2224/05644 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85099 ,  H01L2224/854 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755

Abstract: A packaged vertical semiconductive device including a compressive stress and a method of making such a packaged vertical semiconductive device are disclosed. In one embodiment an assembled device includes a carrier, a connection layer disposed on the carrier, the connection layer having a first height, and a chip disposed on the connection layer, the chip having a second height, wherein the second height is smaller than the first height.

Abstract translation: 公开了包括压缩应力的封装的垂直半导体器件和制造这种封装的垂直半导体器件的方法。 在一个实施例中，组装的装置包括载体，设置在载体上的连接层，具有第一高度的连接层和设置在连接层上的芯片，该芯片具有第二高度，其中第二高度小于 第一高度