公开(公告)号：US12261146B2

公开(公告)日：2025-03-25

申请号：US18336067

申请日：2023-06-16

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber

IPC: H01L23/00

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

公开(公告)号：US11984392B2

公开(公告)日：2024-05-14

申请号：US17459296

申请日：2021-08-27

Applicant: Infineon Technologies AG

Inventor： Chee Yang Ng ,  Stefan Woetzel ,  Edward Fuergut ,  Thai Kee Gan ,  Chee Hong Lee ,  Jayaganasan Narayanasamy ,  Ralf Otremba

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/373 ,  H01L23/492 ,  H01L23/538 ,  H01L29/66 ,  H01L23/31

CPC classification number: H01L23/49844 ,  H01L23/3735 ,  H01L23/4924 ,  H01L23/5383 ,  H01L24/05 ,  H01L24/08 ,  H01L24/14 ,  H01L24/16 ,  H01L29/66431 ,  H01L23/3185 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L2224/0556 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/32227 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091

Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

公开(公告)号：US11915999B2

公开(公告)日：2024-02-27

申请号：US18103865

申请日：2023-01-31

Applicant: Infineon Technologies AG

Inventor： Tomasz Naeve ,  Ralf Otremba ,  Thorsten Scharf ,  Markus Dinkel ,  Martin Gruber ,  Elvir Kahrimanovic

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/40 ,  H01L25/065 ,  H01L25/075 ,  H01L25/04 ,  H02P27/06

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4012 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L25/043 ,  H01L25/0655 ,  H01L25/0756 ,  H01L2924/181 ,  H02P27/06 ,  H02P2201/03

Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

公开(公告)号：US20230187326A1

公开(公告)日：2023-06-15

申请号：US18103865

申请日：2023-01-31

Applicant: Infineon Technologies AG

Inventor： Tomasz Naeve ,  Ralf Otremba ,  Thorsten Scharf ,  Markus Dinkel ,  Martin Gruber ,  Elvir Kahrimanovic

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/49568 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49575 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/49562 ,  H01L23/3107 ,  H01L25/0655 ,  H02P2201/03 ,  H02P27/06

Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

公开(公告)号：US11600558B2

公开(公告)日：2023-03-07

申请号：US16845304

申请日：2020-04-10

Applicant: Infineon Technologies AG

Inventor： Tomasz Naeve ,  Ralf Otremba ,  Thorsten Scharf ,  Markus Dinkel ,  Martin Gruber ,  Elvir Kahrimanovic

IPC: H01L23/48 ,  H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H02P27/06

Abstract: A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact structure. The semiconductor chip is arranged with its front side facing the carrier with the first connecting pad over the recess and with the second connecting pad contacting the pad contact area. The clip is arranged over a back side of the semiconductor chip covering the semiconductor chip where it extends over the recess. The electrically conductive contact structure electrically conductively connects the first connecting pad with the first external connection.

公开(公告)号：US11424217B2

公开(公告)日：2022-08-23

申请号：US16943084

申请日：2020-07-30

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Ralf Otremba ,  Stefan Schwab

IPC: H01L23/00 ,  H01L29/45

Abstract: An arrangement is disclosed. In one example, the arrangement of a conductor and an aluminum layer soldered together comprises a substrate and the aluminum layer disposed over the substrate. The aluminum forms a first bond metal. An intermetallic compound layer is disposed over the aluminum layer. A solder layer is disposed over the intermetallic compound layer, wherein the solder comprises a low melting majority component. The conductor is disposed over the solder layer, wherein the conductor has a soldering surface which comprises a second bond metal. The intermetallic compound comprises aluminum and the second bond metal and is predominantly free of the low melting majority component.

公开(公告)号：US11355424B2

公开(公告)日：2022-06-07

申请号：US17012198

申请日：2020-09-04

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Teck Sim Lee ,  Lee Shuang Wang ,  Mohd Hasrul Zulkifli

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal.

公开(公告)号：US20220157686A1

公开(公告)日：2022-05-19

申请号：US17097098

申请日：2020-11-13

Applicant: Infineon Technologies AG

Inventor： Jo Ean Joanna Chye ,  Edward Fuergut ,  Ralf Otremba

IPC: H01L23/367 ,  H01L23/31

Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.

公开(公告)号：US20200328141A1

公开(公告)日：2020-10-15

申请号：US16845304

申请日：2020-04-10

Applicant: Infineon Technologies AG

Inventor： Tomasz Naeve ,  Ralf Otremba ,  Thorsten Scharf ,  Markus Dinkel ,  Martin Gruber ,  Elvir Kahrimanovic

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact structure. The semiconductor chip is arranged with its front side facing the carrier with the first connecting pad over the recess and with the second connecting pad contacting the pad contact area. The clip is arranged over a back side of the semiconductor chip covering the semiconductor chip where it extends over the recess. The electrically conductive contact structure electrically conductively connects the first connecting pad with the first external connection.

公开(公告)号：US20200243480A1

公开(公告)日：2020-07-30

申请号：US16820057

申请日：2020-03-16

Applicant: Infineon Technologies AG

Inventor： Edmund Riedl ,  Wu Hu Li ,  Alexander Heinrich ,  Ralf Otremba ,  Werner Reiss

IPC: H01L23/00 ,  H01L23/498 ,  B23K35/26 ,  B23K1/00 ,  B23K35/28 ,  B23K1/20 ,  B23K101/38

Abstract: A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.