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公开(公告)号：US11787686B2
公开(公告)日：2023-10-17
申请号：US17395038
申请日：2021-08-05
Applicant: Infineon Technologies AG
Inventor： Andre Brockmeier , Wolfgang Friza , Daniel Maurer
CPC classification number: B81B7/0006 , B81B7/0009 , B81C1/00246 , B81C1/00476 , B81C1/00595
Abstract: In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.
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公开(公告)号：US20210363002A1
公开(公告)日：2021-11-25
申请号：US17395038
申请日：2021-08-05
Applicant: Infineon Technologies AG
Inventor： Andre Brockmeier , Wolfgang Friza , Daniel Maurer
Abstract: In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.
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公开(公告)号：US10766766B2
公开(公告)日：2020-09-08
申请号：US16108538
申请日：2018-08-22
Applicant: Infineon Technologies AG
Inventor： Andre Brockmeier , Wolfgang Friza , Daniel Maurer
Abstract: In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.
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公开(公告)号：US20190071303A1
公开(公告)日：2019-03-07
申请号：US16108538
申请日：2018-08-22
Applicant: Infineon Technologies AG
Inventor： Andre Brockmeier , Wolfgang Friza , Daniel Maurer
CPC classification number: B81B7/0006 , B81B7/0009 , B81C1/00246 , B81C1/00476 , B81C1/00595
Abstract: In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.
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公开(公告)号：US20170297899A1
公开(公告)日：2017-10-19
申请号：US15629834
申请日：2017-06-22
Applicant: Infineon Technologies AG
Inventor： Alfons Dehe , Stefan Barzen , Ulrich Krumbein , Wolfgang Friza , Wolfgang Klein
CPC classification number: B81B3/0072 , B81B2203/0109 , B81C1/00325
Abstract: A method for forming a microelectromechanical device may provide forming a first layer at least one of in or over a semiconductor carrier; forming a second layer at least one of in or over at least a central region of the first layer, such that a peripheral region of the first layer is at least partially free of the second layer; removing material under at least a central region of the second layer to release at least one of the central region of the second layer or a central region of the first layer; and/or removing material under at least the peripheral region of the first layer to such that the second layer is supported by the semiconductor carrier via the first layer.
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Patent Agency Ranking
公开(公告)号：US20170247245A1
公开(公告)日：2017-08-31
申请号：US15054310
申请日：2016-02-26
Applicant: Infineon Technologies AG
Inventor： Alfons Dehe , Stefan Barzen , Ulrich Krumbein , Wolfgang Friza , Wolfgang Klein
CPC classification number: B81B3/0072 , B81B2203/0109 , B81C1/00325
Abstract: A microelectromechanical device may include: a semiconductor carrier; a microelectromechanical element disposed in a position distant to the semiconductor carrier; wherein the microelectromechanical element is configured to generate or modify an electrical signal in response to a mechanical signal and/or is configured to generate or modify a mechanical signal in response to an electrical signal; at least one contact pad, which is electrically connected to the microelectromechanical element for transferring the electrical signal between the contact pad and the microelectromechanical element; and a connection structure which extends from the semiconductor carrier to the microelectromechanical element and mechanically couples the microelectromechanical element with the semiconductor carrier.
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公开(公告)号：US09745188B1
公开(公告)日：2017-08-29
申请号：US15054310
申请日：2016-02-26
Applicant: Infineon Technologies AG
Inventor： Alfons Dehe , Stefan Barzen , Ulrich Krumbein , Wolfgang Friza , Wolfgang Klein
CPC classification number: B81B3/0072 , B81B2203/0109 , B81C1/00325
Abstract: A microelectromechanical device may include: a semiconductor carrier; a microelectromechanical element disposed in a position distant to the semiconductor carrier; wherein the microelectromechanical element is configured to generate or modify an electrical signal in response to a mechanical signal and/or is configured to generate or modify a mechanical signal in response to an electrical signal; at least one contact pad, which is electrically connected to the microelectromechanical element for transferring the electrical signal between the contact pad and the microelectromechanical element; and a connection structure which extends from the semiconductor carrier to the microelectromechanical element and mechanically couples the microelectromechanical element with the semiconductor carrier.
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公开(公告)号：US09363609B2
公开(公告)日：2016-06-07
申请号：US14044654
申请日：2013-10-02
Applicant: Infineon Technologies AG
Inventor： Wolfgang Friza , Thomas Grille , Klaus Muemmler , Guenter Ziegler , Carsten Ahrens
CPC classification number: H04R23/00 , B81B2201/0257 , B81B2203/0118 , B81B2203/0315 , B81C1/00047 , B81C1/00936 , B81C2201/0109 , G01L9/0042 , H04R19/005 , H04R31/006
Abstract: Embodiments show a method for fabricating a cavity structure, a semiconductor structure, a cavity structure for a semiconductor device and a semiconductor microphone fabricated by the same. In some embodiments the method for fabricating a cavity structure comprises providing a first layer, depositing a carbon layer on the first layer, covering at least partially the carbon layer with a second layer to define the cavity structure, removing by means of dry etching the carbon layer between the first and second layer so that the cavity structure is formed.
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19.发明公开公开(公告)号：US20230224657A1
公开(公告)日：2023-07-13
申请号：US18184197
申请日：2023-03-15
Applicant: Infineon Technologies AG
Inventor： Alfons Dehe , Stefan Barzen , Wolfgang Friza , Wolfgang Klein
CPC classification number: H04R31/003 , H04R19/005 , H04R19/04 , B81B3/0072 , B81C1/00182 , H04R7/14 , B81C1/00158 , B81B3/001 , B81C1/00666 , B81B2201/0257
Abstract: In one embodiment, a method of manufacturing a semiconductor device includes oxidizing a substrate to form local oxide regions that extend above a top surface of the substrate. A membrane layer is formed over the local oxide regions and the top surface of the substrate. A portion of the substrate under the membrane layer is removed. The local oxide regions under the membrane layer are removed.
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公开(公告)号：US20210017019A1
公开(公告)日：2021-01-21
申请号：US17065156
申请日：2020-10-07
Applicant: Infineon Technologies AG
Inventor： Alfred Sigl , Wolfgang Friza , Stefan Geissler
IPC: B81C1/00 , H04R19/00 , H01L21/311 , H01L21/677 , H01L23/00
Abstract: A method for producing a thin-film layer includes providing a layer stack on a carrier substrate, wherein the layer stack includes a carrier layer and a sacrificial layer, and wherein the sacrificial layer includes areas in which the carrier layer is exposed. The method includes providing the thin-film layer on the layer stack, such that the thin-film layer bears on the sacrificial layer and, in the areas of the sacrificial layer in which the carrier layer is exposed, against the carrier layer. The method includes at least partly removing the sacrificial layer from the thin-film layer in order to eliminate a contact between the thin-film layer and the sacrificial layer in some areas. The method also includes detaching the thin-film layer from the carrier layer.
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