公开(公告)号：US09559726B2

公开(公告)日：2017-01-31

申请号：US14740100

申请日：2015-06-15

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Asaf Rubinstein ,  Julius Yuli Mandelblat

IPC: H03M13/00 ,  H03M13/29 ,  G06F11/10

CPC classification number: H03M13/2942 ,  G06F11/1076 ,  H03M13/05 ,  H03M13/19 ,  H03M13/451

Abstract: Integrated circuits, systems and methods are disclosed in which data bits protected by error correction code (ECC) detection and correction may be increased such that a combination of primary and additional bits may also be ECC protected using existing ECC allocation, without affecting ECC capabilities. For example, the additional bits may be encoded into phantom bits that are in turn used in combination with the primary bits, to generate an ECC. This ECC may then be combined with the primary bits to form a code word. The code word may be transmitted (or stored) so that when the data bits are received (or retrieved), assumed values of the phantom bits may be decoded, using the ECC, back into the additional bits without the phantom bits or the additional bits ever having transmitted (or stored).

Abstract translation: 公开了集成电路，系统和方法，其中可以增加由纠错码（ECC）检测和校正保护的数据位，使得使用现有ECC分配也可以对主位和附加位的组合进行ECC保护，而不影响ECC能力。 例如，附加比特可以被编码成虚拟比特，其依次与主比特结合使用，以生成ECC。 然后可以将该ECC与主要位组合以形成代码字。 代码字可以被发送（或存储），使得当数据位被接收（或检索）时，可以使用ECC将假想的虚拟位值解码为没有幻像位或附加位的附加位 曾经传播（或存储）。

公开(公告)号：US20160335187A1

公开(公告)日：2016-11-17

申请号：US14709323

申请日：2015-05-11

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Anant V. Nori ,  Supratik Majumder ,  Yoav Lossin ,  Asaf Rubinstein

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0864 ,  G06F12/0851 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/6032 ,  Y02D10/13

Abstract: Integrated circuits are provided which create page locality in cache controllers that allocate entries to set-associative cache, which includes data storage for a plurality of Sets of Ways. A plurality of cache controllers may be interleaved with a processor and device(s), and allocate to any pages in the cache. A cache controller may select a Way from a Set to which to allocate new entries in the set-associative cache and bias selection of the Way according to a plurality of upper address bits (or other function). These bits may be identical at the cache controller during sequential memory transactions. A processor may determine the bias centrally, and inform the cache controllers of the selected Set and Way. Other functions, algorithms or approaches may be chosen to influence bias of Way selection, such as based on analysis of metadata belonging to cache controllers used for making Way allocation selections.

Abstract translation: 提供集成电路，其在高速缓存控制器中创建页面位置，其将条目分配给设置关联高速缓存，其包括用于多个方式集合的数据存储。 多个高速缓存控制器可以与处理器和设备进行交织，并且分配给高速缓存中的任何页面。 高速缓存控制器可以根据多个高位地址位（或其他功能），从集合中选择一个路径，该集合将在集合相关高速缓存中分配新条目，并根据多个高位地址位（或其他功能）偏移选择道。 这些位在顺序存储器事务期间在高速缓存控制器上可以是相同的。 处理器可以集中地确定偏差，并且向高速缓存控制器通知所选择的集合和方式。 可以选择其他功能，算法或方法来影响Way选择的偏向，例如基于属于用于进行Way分配选择的高速缓存控制器的元数据的分析。

公开(公告)号：US11042315B2

公开(公告)日：2021-06-22

申请号：US15940499

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Christopher E. Cox ,  Navneet Dour ,  Asaf Rubinstein ,  Israel Diamand

IPC: G06F3/06 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/42

Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

公开(公告)号：US10678706B2

公开(公告)日：2020-06-09

申请号：US15920145

申请日：2018-03-13

Applicant: INTEL CORPORATION

Inventor： Zvika Greenfield ,  Eshel Serlin ,  Asaf Rubinstein ,  Eli Abadi

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/123 ,  G06F12/126 ,  G06F11/10 ,  G06F12/121

Abstract: Embodiments of the present disclosure are directed towards a computing device having a cache memory device with a scrubber logic. In some embodiments, the scrubber logic controller may be coupled with the cache device, and may perform a selection for eviction from the cache device a portion of data stored in the cache device, based at least in part on one or more selection criteria, at a dynamically adjusted level of aggressiveness of the selection performance. The scrubber logic controller may adjust the level of aggressiveness of the selection performance, based at least in part on a determined time left to complete the selection performance at a current level of aggressiveness. Other embodiments may be described and/or claimed.

公开(公告)号：US20170338837A1

公开(公告)日：2017-11-23

申请号：US15412763

申请日：2017-01-23

Applicant: INTEL CORPORATION

Inventor： Daniel Greenspan ,  Asaf Rubinstein ,  Julius Yuli Mandelblat

IPC: H03M13/29 ,  H03M13/05 ,  H03M13/45 ,  G06F11/10 ,  H03M13/19

CPC classification number: H03M13/2942 ,  G06F11/1076 ,  H03M13/05 ,  H03M13/19 ,  H03M13/451

Abstract: Integrated circuits, systems and methods are disclosed in which data bits protected by error correction code (ECC) detection and correction may be increased such that a combination of primary and additional bits may also be ECC protected using existing ECC allocation, without affecting ECC capabilities. For example, the additional bits may be encoded into phantom bits that are in turn used in combination with the primary bits, to generate an ECC. This ECC may then be combined with the primary bits to form a code word. The code word may be transmitted (or stored) so that when the data bits are received (or retrieved), assumed values of the phantom bits may be decoded, using the ECC, back into the additional bits without the phantom bits or the additional bits ever having transmitted (or stored).

公开(公告)号：US09710054B2

公开(公告)日：2017-07-18

申请号：US14634777

申请日：2015-02-28

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

公开(公告)号：US20160365876A1

公开(公告)日：2016-12-15

申请号：US14740100

申请日：2015-06-15

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Asaf Rubinstein ,  Julius Yuli Mandelblat

IPC: H03M13/29 ,  G06F11/10

CPC classification number: H03M13/2942 ,  G06F11/1076 ,  H03M13/05 ,  H03M13/19 ,  H03M13/451

Abstract: Integrated circuits, systems and methods are disclosed in which data bits protected by error correction code (ECC) detection and correction may be increased such that a combination of primary and additional bits may also be ECC protected using existing ECC allocation, without affecting ECC capabilities. For example, the additional bits may be encoded into phantom bits that are in turn used in combination with the primary bits, to generate an ECC. This ECC may then be combined with the primary bits to form a code word. The code word may be transmitted (or stored) so that when the data bits are received (or retrieved), assumed values of the phantom bits may be decoded, using the ECC, back into the additional bits without the phantom bits or the additional bits ever having transmitted (or stored).

Abstract translation: 公开了集成电路，系统和方法，其中可以增加由纠错码（ECC）检测和校正保护的数据位，使得使用现有ECC分配也可以对主位和附加位的组合进行ECC保护，而不影响ECC能力。 例如，附加比特可以被编码成虚拟比特，其依次与主比特结合使用，以生成ECC。 然后可以将该ECC与主要位组合以形成代码字。 代码字可以被发送（或存储），使得当数据位被接收（或检索）时，可以使用ECC将假想的虚拟位值解码为没有幻像位或附加位的附加位 曾经传播（或存储）。

公开(公告)号：US20240220410A1

公开(公告)日：2024-07-04

申请号：US18089757

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ayan Mandal ,  Prasanna Pandit ,  Neetu Jindal ,  Israel Diamand ,  Asaf Rubinstein ,  Leon Polishuk ,  Oz Shitrit

IPC: G06F12/0806

CPC classification number: G06F12/0806 ,  G06F2212/62

Abstract: Methods and apparatus relating to leveraging system cache for performance cores are described. In an embodiment, a system cache stores one or more cachelines that are to be evicted from a processor cache. Logic circuitry determines whether to store the one or more cachelines in the system cache based at least in part on comparison of a threshold value with a hit rate associated with the one or more cachelines. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240220408A1

公开(公告)日：2024-07-04

申请号：US18089782

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Nadav Bonen ,  Israel Diamand ,  Julius Mandelblat ,  Asaf Rubinstein ,  Igor Brainman

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1016

Abstract: Methods and apparatus relating to dynamic allocation schemes applied to a memory side cache for bandwidth and/or performance optimization are described. In an embodiment, a memory side cache stores a portion of data to be stored in a main memory. Logic circuitry determines whether to allocate a portion of the memory side cache for use by a device. The remaining portion of the memory side cache is to be used by a processor. The allocated portion of the memory side cache is reallocated for use by the processor in response to a determination that the allocated portion of the memory side cache is no longer to be used by the device. Other embodiments are also disclosed and claimed.

公开(公告)号：US10304418B2

公开(公告)日：2019-05-28

申请号：US15276856

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Randy Osborne ,  Zvika Greenfield ,  Israel Diamand ,  Asaf Rubinstein

IPC: G06F3/14 ,  G09G5/39 ,  G09G5/393 ,  G06F12/0895

Abstract: An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.