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    VERTICAL DIODES IN STACKED TRANSISTOR TECHNOLOGIES
    11.
    发明申请
    VERTICAL DIODES IN STACKED TRANSISTOR TECHNOLOGIES 有权

    公开(公告)号：US20230089395A1

    公开(公告)日：2023-03-23

    申请号：US17448373

    申请日：2021-09-22

    Applicant: INTEL CORPORATION

    Inventor： Benjamin Orr ,  Nicholas A. Thomson ,  Ayan Kar ,  Nathan D. Jack ,  Kalyan C. Kolluru ,  Patrick Morrow ,  Cheng-Ying Huang ,  Charles C. Kuo

    IPC: H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

    Abstract: Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source/drain regions are merged) or a PIN junction (e.g., first and second source/drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).

    TECHNIQUES AND CONFIGURATIONS FOR STACKING TRANSISTORS OF AN INTEGRATED CIRCUIT DEVICE
    17.
    发明申请
    TECHNIQUES AND CONFIGURATIONS FOR STACKING TRANSISTORS OF AN INTEGRATED CIRCUIT DEVICE 审中-公开
    集成电路器件堆叠晶体管的技术和配置

    公开(公告)号：US20160064545A1

    公开(公告)日：2016-03-03

    申请号：US14938739

    申请日：2015-11-11

    Applicant: INTEL CORPORATION

    Inventor： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12

    CPC classification number: H01L29/785 ,  G11C11/412 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1211 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

    Abstract: Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例提供了用于堆叠存储器件的晶体管的技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的多个翅片结构，其中，多个翅片结构的单个翅片结构包括设置在半导体衬底上的第一隔离层， 第一隔离层，设置在第一沟道层上的第二隔离层和设置在第二隔离层上的第二沟道层，以及与第一沟道层电容耦合以控制通过第一沟道层的电流的栅极端子 用于第一晶体管，并与第二沟道层电容耦合，以控制通过第二沟道层的电流流向第二晶体管。 可以描述和/或要求保护其他实施例。

    Self-aligned embedded phase change memory cell having a fin shaped bottom electrode
    18.
    发明授权
    Self-aligned embedded phase change memory cell having a fin shaped bottom electrode 有权

    公开(公告)号：US11264428B2

    公开(公告)日：2022-03-01

    申请号：US16630346

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Charles C. Kuo

    IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00

    Abstract: An integrated circuit comprising a self-aligned embedded phase change memory cell is described. In an example, the integrated circuit includes a bottom electrode. A conductive line is above the bottom electrode along a first direction above a substrate. A memory element is coupled between the bottom electrode and the conductive line, the memory element comprising a phase change material layer that is self-aligned with the conductive line.

    Techniques for forming spin-transfer torque memory having a dot-contacted free magnetic layer
    19.
    发明授权
    Techniques for forming spin-transfer torque memory having a dot-contacted free magnetic layer 有权

    公开(公告)号：US10707409B2

    公开(公告)日：2020-07-07

    申请号：US15882546

    申请日：2018-01-29

    Applicant: INTEL CORPORATION

    Inventor： Charles C. Kuo ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  David L. Kencke ,  Satyarth Suri ,  Robert S. Chau

    IPC: H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

    Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

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